From ea3cc3231c0b74afd03b74a49a7f2a13eba0bc21 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Tue, 17 Jun 2025 13:15:20 -0700 Subject: [PATCH] mb/intel/ptlrvp: Remove power limit constraints This commit eliminates the power limit constraints initially adopted from the Fatcat board's codebase. These constraints are tailored for factory-specific scenarios, which are irrelevant to the Intel Panther Lake RVP (PTLRVP) board's use case. Change-Id: I3e4dfe85a2677ad3998fd6c0f9a59fa966587c59 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/88132 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- .../variants/baseboard/ptlrvp/Makefile.mk | 1 - .../variants/baseboard/ptlrvp/ramstage.c | 62 ------------------- 2 files changed, 63 deletions(-) delete mode 100644 src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk index ff6ed05ded..be05cd4e5c 100644 --- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk +++ b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/Makefile.mk @@ -1,4 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only romstage-y += memory.c -ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ramstage.c diff --git a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c b/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c deleted file mode 100644 index 6c7668fa4b..0000000000 --- a/src/mainboard/intel/ptlrvp/variants/baseboard/ptlrvp/ramstage.c +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include - -/* - * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), - * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) - */ -const struct cpu_tdp_power_limits power_optimized_limits[] = { - { - .mch_id = PCI_DID_INTEL_PTL_H_ID_1, - .cpu_tdp = TDP_25W, - .power_limits_index = PTL_H_1_CORE, - .pl1_min_power = 10000, - .pl1_max_power = 25000, - .pl2_min_power = 50000, - .pl2_max_power = 50000, - .pl4_power = 65000 - }, - { - .mch_id = PCI_DID_INTEL_PTL_H_ID_2, - .cpu_tdp = TDP_25W, - .power_limits_index = PTL_H_1_CORE, - .pl1_min_power = 10000, - .pl1_max_power = 25000, - .pl2_min_power = 50000, - .pl2_max_power = 50000, - .pl4_power = 65000 - }, - { - .mch_id = PCI_DID_INTEL_PTL_H_ID_3, - .cpu_tdp = TDP_25W, - .power_limits_index = PTL_H_2_CORE, - .pl1_min_power = 10000, - .pl1_max_power = 25000, - .pl2_min_power = 50000, - .pl2_max_power = 50000, - .pl4_power = 65000 - }, - { - .mch_id = PCI_DID_INTEL_PTL_H_ID_4, - .cpu_tdp = TDP_25W, - .power_limits_index = PTL_H_2_CORE, - .pl1_min_power = 10000, - .pl1_max_power = 25000, - .pl2_min_power = 50000, - .pl2_max_power = 50000, - .pl4_power = 65000 - }, -}; - -void baseboard_devtree_update(void) -{ - /* Don't optimize the power limit if booting with barrel attached */ - if (CONFIG(BOARD_INTEL_MODEL_PTLRVP) && google_chromeec_is_barrel_charger_present()) - return; - - if (!google_chromeec_is_battery_present()) - variant_update_cpu_power_limits(power_optimized_limits, - ARRAY_SIZE(power_optimized_limits)); -}