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UPSTREAM: soc/intel/braswell: Hide some Kconfig options in menuconfig

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Don't allow the user to set PCIe configspace base address.

Don't allow the user to set the DCACHE size and base.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ic14c6b908edb31d371081c49b9388265eda21151
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 9c27eda052
Original-Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20181
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539217
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-06-13 14:47:28 +02:00 • committed by chrome-bot
commit e95bc87261
1 changed files with 3 additions and 3 deletions
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6
src/soc/intel/braswell/Kconfig
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@ -55,7 +55,7 @@ config BOOTBLOCK_CPU_INIT
default "soc/intel/braswell/bootblock/bootblock.c"
config MMCONF_BASE_ADDRESS
hex "PCIe CFG Base Address"
hex
default 0xe0000000
config MAX_CPUS
@ -88,11 +88,11 @@ config SMM_RESERVED_SIZE
#
config DCACHE_RAM_BASE
hex "Temporary RAM Base Address"
hex
default 0xfef00000
config DCACHE_RAM_SIZE
hex "Temporary RAM Size"
hex
default 0x4000
help
The size of the cache-as-ram region required during bootblock