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UPSTREAM: soc/intel/skylake: Don't allow user to change DCACHE base and size

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BUG=none
BRANCH=none
TEST=none

Change-Id: I584088ba0b02411b8c59c6a5d84d1aa27bfd883f
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 432ac615d0
Original-Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1
Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-on: https://review.coreboot.org/20180
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/539216
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Arthur Heymans 2017-06-13 14:17:05 +02:00 • committed by chrome-bot
commit 993ac31838
1 changed files with 2 additions and 2 deletions
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4
src/soc/intel/skylake/Kconfig
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@ -127,11 +127,11 @@ config CPU_ADDR_BITS
default 36
config DCACHE_RAM_BASE
hex "Base address of cache-as-RAM"
hex
default 0xfef00000
config DCACHE_RAM_SIZE
hex "Length in bytes of cache-as-RAM"
hex
default 0x40000
help
The size of the cache-as-ram region required during bootblock