From e95bc87261e7692c1e74240f1564cd307aaf4686 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 13 Jun 2017 14:47:28 +0200 Subject: [PATCH] UPSTREAM: soc/intel/braswell: Hide some Kconfig options in menuconfig Don't allow the user to set PCIe configspace base address. Don't allow the user to set the DCACHE size and base. BUG=none BRANCH=none TEST=none Change-Id: Ic14c6b908edb31d371081c49b9388265eda21151 Signed-off-by: Patrick Georgi Original-Commit-Id: 9c27eda052fdf189288dc12223c0673109576725 Original-Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84 Original-Signed-off-by: Arthur Heymans Original-Reviewed-on: https://review.coreboot.org/20181 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Sumeet R Pawnikar Reviewed-on: https://chromium-review.googlesource.com/539217 Commit-Ready: Patrick Georgi Tested-by: Patrick Georgi Reviewed-by: Patrick Georgi --- src/soc/intel/braswell/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 520253add0..36af3fef09 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -55,7 +55,7 @@ config BOOTBLOCK_CPU_INIT default "soc/intel/braswell/bootblock/bootblock.c" config MMCONF_BASE_ADDRESS - hex "PCIe CFG Base Address" + hex default 0xe0000000 config MAX_CPUS @@ -88,11 +88,11 @@ config SMM_RESERVED_SIZE # config DCACHE_RAM_BASE - hex "Temporary RAM Base Address" + hex default 0xfef00000 config DCACHE_RAM_SIZE - hex "Temporary RAM Size" + hex default 0x4000 help The size of the cache-as-ram region required during bootblock