From e63e54e0e956c549c2a3e422b1f406c56210ff8e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Mon, 3 Mar 2025 16:11:00 +0100 Subject: [PATCH] mb/novacustom/mtl-h/devicetree.cb: Disable detect flag on PCIe CLKREQs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Probing the clock request signal is not required on this board and with the SSD models the board is sold with. Change-Id: I51b0d0f2b390912cf8fff45d736e317de31863ed Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/coreboot/+/86694 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/novacustom/mtl-h/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb index 22bf4068aa..ef29ec18ce 100644 --- a/src/mainboard/novacustom/mtl-h/devicetree.cb +++ b/src/mainboard/novacustom/mtl-h/devicetree.cb @@ -78,7 +78,7 @@ chip soc/intel/meteorlake register "pcie_rp[PCH_RP(10)]" = "{ .clk_src = 8, .clk_req = 8, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip soc/intel/common/block/pcie/rtd3 register "is_storage" = "true" @@ -93,7 +93,7 @@ chip soc/intel/meteorlake register "pcie_rp[PCH_RP(11)]" = "{ .clk_src = 7, .clk_req = 7, - .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + .flags = PCIE_RP_LTR | PCIE_RP_AER, }" chip soc/intel/common/block/pcie/rtd3 register "is_storage" = "true"