diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c
index 50628a7d98..00099794d8 100644
--- a/src/soc/intel/skylake/gpio.c
+++ b/src/soc/intel/skylake/gpio.c
@@ -57,6 +57,7 @@ static const struct pad_community skl_gpio_communities[] = {
 		.last_pad = GPP_B23,
 		.num_gpi_regs = NUM_GPIO_COM0_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM0,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
@@ -81,6 +82,7 @@ static const struct pad_community skl_gpio_communities[] = {
 #endif
 		.num_gpi_regs = NUM_GPIO_COM1_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM1,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
@@ -106,6 +108,7 @@ static const struct pad_community skl_gpio_communities[] = {
 #endif
 		.num_gpi_regs = NUM_GPIO_COM3_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM3,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
@@ -126,6 +129,7 @@ static const struct pad_community skl_gpio_communities[] = {
 		.last_pad = GPD11,
 		.num_gpi_regs = NUM_GPIO_COM2_GPI_REGS,
 		.pad_cfg_base = PAD_CFG_BASE,
+		.pad_cfg_lock_offset = PAD_CFG_LOCK_OFFSET_COM2,
 		.host_own_reg_0 = HOSTSW_OWN_REG_0,
 		.gpi_int_sts_reg_0 = GPI_INT_STS_0,
 		.gpi_int_en_reg_0 = GPI_INT_EN_0,
diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h
index 0e98b89169..f91dd63300 100644
--- a/src/soc/intel/skylake/include/soc/gpio_defs.h
+++ b/src/soc/intel/skylake/include/soc/gpio_defs.h
@@ -209,6 +209,19 @@
 #define  GPIO_DRIVER_IRQ_ROUTE_IRQ14   0
 #define  GPIO_DRIVER_IRQ_ROUTE_IRQ15   8
 #define HOSTSW_OWN_REG_0	0xd0
+
+#if CONFIG(SKYLAKE_SOC_PCH_H)
+#define PAD_CFG_LOCK_OFFSET_COM0 0xa0
+#define PAD_CFG_LOCK_OFFSET_COM1 0x90
+#define PAD_CFG_LOCK_OFFSET_COM2 0x90
+#define PAD_CFG_LOCK_OFFSET_COM3 0x90
+#else
+#define PAD_CFG_LOCK_OFFSET_COM0 0xa0
+#define PAD_CFG_LOCK_OFFSET_COM1 0xa0
+#define PAD_CFG_LOCK_OFFSET_COM2 0xa0
+#define PAD_CFG_LOCK_OFFSET_COM3 0xa0
+#endif /* CONFIG(SKYLAKE_SOC_PCH_H) */
+
 #define PAD_CFG_BASE		0x400
 #define GPI_INT_STS_0		0x100
 #define GPI_INT_EN_0		0x120