erebion/coreboot
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One typo and one change to get our bootblock back into 20k.

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Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@848 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Ronald G. Minnich 2008-08-30 03:42:01 +00:00
commit df00b48496
2 changed files with 2 additions and 2 deletions
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2
arch/x86/stage1_mtrr.c
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@ -63,7 +63,7 @@ void cache_cbmem(int type)
{
/* Enable caching for 0 - 1MB using variable mtrr */
disable_cache();
set_var_mtrr(0, 0x00000000, COREBOOT_MEM_TOPK << 10, type);
set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type);
enable_cache();
}

2
mainboard/amd/serengeti/Makefile
View file

@ -27,13 +27,13 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
$(src)/southbridge/amd/amd8111/stage1_ctrl.c \
$(src)/southbridge/amd/amd8111/stage1_enable_rom.c \
$(src)/northbridge/amd/k8/coherent_ht.c \
$(src)/northbridge/amd/k8/incoherent_ht.c \
$(src)/northbridge/amd/k8/libstage1.c \
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \
$(src)/northbridge/amd/k8/dqs.c \
$(src)/northbridge/amd/k8/reset_test.c \
$(src)/northbridge/amd/k8/incoherent_ht.c \
$(src)/arch/x86/pci_ops_conf1.c \
$(src)/arch/x86/stage1_mtrr.c \
$(src)/southbridge/amd/amd8111/stage1_smbus.c \