diff --git a/arch/x86/stage1_mtrr.c b/arch/x86/stage1_mtrr.c
index 61274c5775..39fdfaa139 100644
--- a/arch/x86/stage1_mtrr.c
+++ b/arch/x86/stage1_mtrr.c
@@ -63,7 +63,7 @@ void cache_cbmem(int type)
 {
 	/* Enable caching for 0 - 1MB using variable mtrr */
 	disable_cache();
-	set_var_mtrr(0, 0x00000000, COREBOOT_MEM_TOPK << 10, type);
+	set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type);
 	enable_cache();
 }
 
diff --git a/mainboard/amd/serengeti/Makefile b/mainboard/amd/serengeti/Makefile
index 23c508d1a5..d038491699 100644
--- a/mainboard/amd/serengeti/Makefile
+++ b/mainboard/amd/serengeti/Makefile
@@ -27,13 +27,13 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
 			$(src)/southbridge/amd/amd8111/stage1_ctrl.c \
 			$(src)/southbridge/amd/amd8111/stage1_enable_rom.c \
 			$(src)/northbridge/amd/k8/coherent_ht.c \
-			$(src)/northbridge/amd/k8/incoherent_ht.c \
 			$(src)/northbridge/amd/k8/libstage1.c \
 
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/raminit.c \
 			$(src)/northbridge/amd/k8/dqs.c \
 			$(src)/northbridge/amd/k8/reset_test.c \
+			$(src)/northbridge/amd/k8/incoherent_ht.c \
 			$(src)/arch/x86/pci_ops_conf1.c \
 			$(src)/arch/x86/stage1_mtrr.c \
 			$(src)/southbridge/amd/amd8111/stage1_smbus.c \