diff --git a/src/mainboard/lenovo/m900_tiny/Makefile.mk b/src/mainboard/lenovo/m900_tiny/Makefile.mk index 3b5a2a27a5..d016e93f49 100644 --- a/src/mainboard/lenovo/m900_tiny/Makefile.mk +++ b/src/mainboard/lenovo/m900_tiny/Makefile.mk @@ -12,3 +12,5 @@ ramstage-y += gpio.c ramstage-y += hda_verb.c ramstage-y += ramstage.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/m900_tiny/gpio.c b/src/mainboard/lenovo/m900_tiny/gpio.c index 4c4bac4b8e..101f47b673 100644 --- a/src/mainboard/lenovo/m900_tiny/gpio.c +++ b/src/mainboard/lenovo/m900_tiny/gpio.c @@ -91,7 +91,7 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPP_D ------- */ PAD_NC(GPP_D0, NONE), - PAD_NC(GPP_D1, NONE), + PAD_CFG_NF(GPP_D1, NONE, DEEP, NF4), /* PW_LED# (blink mode)*/ PAD_NC(GPP_D2, NONE), PAD_NC(GPP_D3, NONE), PAD_NC(GPP_D4, NONE), diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 7eadabe2a2..92ef6b8e67 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -5,8 +5,10 @@ #include #include #include +#include #include #include +#include #include #include #include @@ -73,6 +75,12 @@ static void mainboard_enable(struct device *dev) mainboard_configure_gpios(); devtree_update(); print_board_id(); + /* Configure GPIO community 1 PWM frequency to 0.5Hz, 0% duty cycle */ + pcr_write32(PID_GPIOCOM1, 0x204, (1 << 14)); + /* Set the software update flag */ + pcr_or32(PID_GPIOCOM1, 0x204, (1 << 30)); + /* Enable PWM */ + pcr_or32(PID_GPIOCOM1, 0x204, (1 << 31)); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/m900_tiny/smihandler.c b/src/mainboard/lenovo/m900_tiny/smihandler.c new file mode 100644 index 0000000000..6ae0b36a25 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/smihandler.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* Enable blinking power LED when entering S3 or S4 */ + switch (slp_typ) { + case ACPI_S3: + case ACPI_S4: + /* Configure GPIO community 1 PWM duty cycle to 50% */ + pcr_rmw32(PID_GPIOCOM1, 0x204, 0xffffff00, 0x7f); + /* Set the software update flag */ + pcr_or32(PID_GPIOCOM1, 0x204, (1 << 30)); + break; + default: + break; + } +}