From d97644dd3fe7e830db95b95e00bb5274e4b72fc7 Mon Sep 17 00:00:00 2001 From: Riku Viitanen Date: Wed, 25 Dec 2024 23:38:42 +0200 Subject: [PATCH] mb/asrock: Add Z77 Extreme4 New port based on logs extracted from a board running OEM firmware. VBT extracted from a running system with "intelvbttool --inlegacy". Internal flashing of the entire chip is possible from vendor firmware by overriding the Flash Descriptor. Conveniently, the HDA_SDO pin is connected to one of the unused pins of the PCIE1 slot. Tested: - i7-3770K CPU (native raminit) - 2x8GB: G.skill F3-1600C9-8GAR (@1600MHz) - 4x8GB: Corsair CMY16GX3M2A2400C (@1333MHz) - libgfxinit txtmode with onboard HDMI, DVI and VGA - Gigabit Ethernet - CPU fan - PS/2 keyboard or mouse (but not at the same time) - SeaBIOS 1.17.0 booting to Devuan and Void Linux - All internal SATA ports - Rear USB ports - Line out - me_cleaner - PCIE2 (x16/x8), PCIE3 (x8) and PCIE4 (x1) slots - PCI slots - Suspend and resume (S3) - Serial port header COM1 (including coreboot output) Untested: - Intel VBIOS - Front USB headers - Other fans - LED headers - eSATA, Toslink - PCIE1 (x1) slot Change-Id: Idf028c6d411bd501b73a3c526240d0b1d6ecaa0c Signed-off-by: Riku Viitanen Reviewed-on: https://review.coreboot.org/c/coreboot/+/85772 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph Reviewed-by: Angel Pons --- src/mainboard/asrock/z77_extreme4/Kconfig | 32 ++++ .../asrock/z77_extreme4/Kconfig.name | 4 + src/mainboard/asrock/z77_extreme4/Makefile.mk | 8 + src/mainboard/asrock/z77_extreme4/acpi/ec.asl | 3 + .../asrock/z77_extreme4/acpi/platform.asl | 10 + .../asrock/z77_extreme4/acpi/superio.asl | 11 ++ .../asrock/z77_extreme4/board_info.txt | 7 + .../asrock/z77_extreme4/cmos.default | 8 + src/mainboard/asrock/z77_extreme4/cmos.layout | 86 +++++++++ src/mainboard/asrock/z77_extreme4/data.vbt | Bin 0 -> 3902 bytes .../asrock/z77_extreme4/devicetree.cb | 168 ++++++++++++++++ src/mainboard/asrock/z77_extreme4/dsdt.asl | 28 +++ .../asrock/z77_extreme4/early_init.c | 12 ++ .../asrock/z77_extreme4/gma-mainboard.ads | 17 ++ src/mainboard/asrock/z77_extreme4/gpio.c | 179 ++++++++++++++++++ src/mainboard/asrock/z77_extreme4/hda_verb.c | 52 +++++ src/mainboard/asrock/z77_extreme4/mainboard.c | 15 ++ 17 files changed, 640 insertions(+) create mode 100644 src/mainboard/asrock/z77_extreme4/Kconfig create mode 100644 src/mainboard/asrock/z77_extreme4/Kconfig.name create mode 100644 src/mainboard/asrock/z77_extreme4/Makefile.mk create mode 100644 src/mainboard/asrock/z77_extreme4/acpi/ec.asl create mode 100644 src/mainboard/asrock/z77_extreme4/acpi/platform.asl create mode 100644 src/mainboard/asrock/z77_extreme4/acpi/superio.asl create mode 100644 src/mainboard/asrock/z77_extreme4/board_info.txt create mode 100644 src/mainboard/asrock/z77_extreme4/cmos.default create mode 100644 src/mainboard/asrock/z77_extreme4/cmos.layout create mode 100644 src/mainboard/asrock/z77_extreme4/data.vbt create mode 100644 src/mainboard/asrock/z77_extreme4/devicetree.cb create mode 100644 src/mainboard/asrock/z77_extreme4/dsdt.asl create mode 100644 src/mainboard/asrock/z77_extreme4/early_init.c create mode 100644 src/mainboard/asrock/z77_extreme4/gma-mainboard.ads create mode 100644 src/mainboard/asrock/z77_extreme4/gpio.c create mode 100644 src/mainboard/asrock/z77_extreme4/hda_verb.c create mode 100644 src/mainboard/asrock/z77_extreme4/mainboard.c diff --git a/src/mainboard/asrock/z77_extreme4/Kconfig b/src/mainboard/asrock/z77_extreme4/Kconfig new file mode 100644 index 0000000000..0bc40152fa --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/Kconfig @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_ASROCK_Z77_EXTREME4 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select DRIVERS_ASMEDIA_ASM1061 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SUPERIO_NUVOTON_COMMON_COM_A + select SUPERIO_NUVOTON_NCT6776 + select USE_NATIVE_RAMINIT + +config CBFS_SIZE + default 0x600000 + +config MAINBOARD_DIR + default "asrock/z77_extreme4" + +config MAINBOARD_PART_NUMBER + default "Z77 Extreme4" + +endif diff --git a/src/mainboard/asrock/z77_extreme4/Kconfig.name b/src/mainboard/asrock/z77_extreme4/Kconfig.name new file mode 100644 index 0000000000..e057b6e67d --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_ASROCK_Z77_EXTREME4 + bool "Z77 Extreme4" diff --git a/src/mainboard/asrock/z77_extreme4/Makefile.mk b/src/mainboard/asrock/z77_extreme4/Makefile.mk new file mode 100644 index 0000000000..e4b6fbf0f0 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/asrock/z77_extreme4/acpi/ec.asl b/src/mainboard/asrock/z77_extreme4/acpi/ec.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z77_extreme4/acpi/platform.asl b/src/mainboard/asrock/z77_extreme4/acpi/platform.asl new file mode 100644 index 0000000000..a56d3190bd --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/asrock/z77_extreme4/acpi/superio.asl b/src/mainboard/asrock/z77_extreme4/acpi/superio.asl new file mode 100644 index 0000000000..1eae4b21da --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/acpi/superio.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e + +#define NCT6776_SHOW_SP1 1 +#define NCT6776_SHOW_KBC 1 + +#include "superio/nuvoton/nct6776/acpi/superio.asl" diff --git a/src/mainboard/asrock/z77_extreme4/board_info.txt b/src/mainboard/asrock/z77_extreme4/board_info.txt new file mode 100644 index 0000000000..3819c563b2 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/Z77%20Extreme4/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2012 diff --git a/src/mainboard/asrock/z77_extreme4/cmos.default b/src/mainboard/asrock/z77_extreme4/cmos.default new file mode 100644 index 0000000000..4501aa4904 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/cmos.default @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +boot_option=Fallback +debug_level=Debug +nmi=Disable +power_on_after_fail=Disable +sata_mode=AHCI +gfx_uma_size=64M diff --git a/src/mainboard/asrock/z77_extreme4/cmos.layout b/src/mainboard/asrock/z77_extreme4/cmos.layout new file mode 100644 index 0000000000..0f9de5ed18 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/cmos.layout @@ -0,0 +1,86 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 2 boot_option +388 4 h 0 reboot_counter + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# coreboot config options: southbridge +408 1 e 1 nmi + +409 2 e 4 power_on_after_fail +411 2 e 5 sata_mode + +# coreboot config options: northbridge +416 5 e 6 gfx_uma_size + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations +#ID value text + +# Generic on/off enum +1 0 Disable +1 1 Enable + +# boot_option +2 0 Fallback +2 1 Normal + +# debug_level +3 0 Emergency +3 1 Alert +3 2 Critical +3 3 Error +3 4 Warning +3 5 Notice +3 6 Info +3 7 Debug +3 8 Spew + +# power_on_after_fail +4 0 Disable +4 1 Enable +4 2 Keep + +# sata_mode +5 0 AHCI +5 1 Compatible +5 2 Legacy + +# gfx_uma_size (Intel IGP Video RAM size) +6 0 32M +6 1 64M +6 2 96M +6 3 128M +6 4 160M +6 5 192M +6 6 224M +6 7 256M +6 8 288M +6 9 320M +6 10 352M +6 11 384M +6 12 416M +6 13 448M +6 14 480M +6 15 512M +6 16 1024M + +# ----------------------------------------------------------------- +checksums + +checksum 392 423 984 diff --git a/src/mainboard/asrock/z77_extreme4/data.vbt b/src/mainboard/asrock/z77_extreme4/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..7c43dcf8fece1203883fd8aa78cc0de1ae6e9125 GIT binary patch literal 3902 zcmdT{Z)jUp6hAlbz5Ka(uT5X;n#Qi&&atIk|GZ|kmQwX4O>5I-ZQ5iZ4smIh><@HZ zm;GS_XP;W!M35*l=bRE0#@wf}PlA5fCn=&*hYS%vjNu0vL-t_^j=6a5%WF4QX`?ut z_wl>u+|zS^x%b?2?t5LI3?*26IMg0VhFZh@@hypwSOzqBrm`9PcVZ(>_O=NRDjB}wk>*#FT+{u`>xxJ&aJ)m_27z=1U zT6a(2Nri^{`$o3LBGF(XGBV6Y##lHK560vDTSL+3S!`@%FcOL+`ojt}x6-$N`dDu7 z?mdT?zpn{dG_4g0JD9m-*0(=5-Nu5GlWdIp9AsnJgW24XY^F`2oZu2TMFK!1s3bth z9|3SViR=^yox0!2Bq9ch-bh$j)D4W)cTST8z`+Q!aR+8Gd~Puy zzn$AT!{Tr8F>lQ5SLhy=gIEt*ptGyHr&kY!2L^|tv9UxlwfzO-l~-Sz^}(Gy;ARQI zu7YR~6Z~*ou)ztT8#ajr_|@)&fJ22aB8k|8IPRcu0`WHD1H^g6MZ_0~FA+Z=t|4w9 zenWth0!7py8W4U&0MUyWK*SK+5gEi3!hRU;6m14L%xD?Jl2s)M9ueMZ0^_V@KWo`t zH}QnAQA@flX&TGuibaP5?iRoGLb2$4ny)}d1`G>?Ev7+BMolRQF>9Pa$^BB+xL9+Mk*3#jxzr5Q?su?Bxs@H3W-clZGA!Dcj-dK5HWo31Wd8qT*Ly*ldKpr=kRS_YrhwTZcau3uWTc>T~dBb0(Ecg;v( zUh=4syqTV;+4*Y(K(6yc9o)vJ4)TOS>6ynjM(JrG_cR}8dHicwz?*Qvaf_U+el#_{ zuku>4SlqeR`^=?&<)Yua*lm|8Q@Vz- zUaAgLnxgDws^%#@L)j&&UZ(UX%4}}6#!VaCEbLa3Zkl$p*WK!AH~rYn=H2R#Zu+yE zQCY2*=?0laW%Wgw?vdGBvRaVo1(_|#>NT0(keRBe>lNCju!N%SQs}h8PATengZX<(0q_x|F>5RU&eR-W7MTymELUl#>3a!;8bk9=l@d7e$ zH@Q59<+aKg%r7fhx6hTahUK-*OV_+|`8 zv +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + #include + #include + + Scope (\_SB) + { + Device (PCI0) + { + #include + #include + } + } +} diff --git a/src/mainboard/asrock/z77_extreme4/early_init.c b/src/mainboard/asrock/z77_extreme4/early_init.c new file mode 100644 index 0000000000..ed381c0e7c --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/early_init.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include + +void bootblock_mainboard_early_init(void) +{ + /* Enable early serial */ + if (CONFIG(CONSOLE_SERIAL)) + nuvoton_enable_serial(NCT6776_SP1, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/asrock/z77_extreme4/gma-mainboard.ads b/src/mainboard/asrock/z77_extreme4/gma-mainboard.ads new file mode 100644 index 0000000000..3f217ca730 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z77_extreme4/gpio.c b/src/mainboard/asrock/z77_extreme4/gpio.c new file mode 100644 index 0000000000..7dae62c27b --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/gpio.c @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_OUTPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio12 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio72 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z77_extreme4/hda_verb.c b/src/mainboard/asrock/z77_extreme4/hda_verb.c new file mode 100644 index 0000000000..276145f912 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/hda_verb.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const u32 realtek_alc898_verbs[] = { + AZALIA_SUBVENDOR(0, 0x18491898), + AZALIA_PIN_CFG(0, 0x11, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x18, 0x01a19840), + AZALIA_PIN_CFG(0, 0x19, 0x02a19950), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214120), + AZALIA_PIN_CFG(0, 0x1c, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x4015e601), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), +}; + +static const u32 intel_display_audio_verbs[] = { + AZALIA_SUBVENDOR(3, 0x80860101), + AZALIA_PIN_CFG(3, 0x05, 0x18560010), + AZALIA_PIN_CFG(3, 0x06, 0x58560020), + AZALIA_PIN_CFG(3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +struct azalia_codec mainboard_azalia_codecs[] = { + { + .name = "Realtek ALC898", + .vendor_id = 0x10ec0899, + .subsystem_id = 0x18491898, + .address = 0, + .verbs = realtek_alc898_verbs, + .verb_count = ARRAY_SIZE(realtek_alc898_verbs), + }, + { + .name = "Intel Display Audio (HDMI)", + .vendor_id = 0x80862806, + .subsystem_id = 0x80860101, + .address = 3, + .verbs = intel_display_audio_verbs, + .verb_count = ARRAY_SIZE(intel_display_audio_verbs), + }, + { /* terminator */ } +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z77_extreme4/mainboard.c b/src/mainboard/asrock/z77_extreme4/mainboard.c new file mode 100644 index 0000000000..c11607a3e1 --- /dev/null +++ b/src/mainboard/asrock/z77_extreme4/mainboard.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_CRT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +};