diff --git a/Makefile.inc b/Makefile.inc
index 4d46ebb61e..da50cbdfb4 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -322,7 +322,7 @@ clean-abuild:
 	rm -rf coreboot-builds
 
 clean-for-update-target:
-	rm -f $(obj)/coreboot_ram* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a
+	rm -f $(obj)/ramstage* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a
 	rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.*
 	rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript
 	rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot
diff --git a/src/Kconfig b/src/Kconfig
index 88baa6b746..c2b3dd7847 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -173,7 +173,7 @@ config INCLUDE_CONFIG_FILE
 	    Name                           Offset     Type         Size
 	    cmos_layout.bin                0x0        cmos layout  1159
 	    fallback/romstage              0x4c0      stage        339756
-	    fallback/coreboot_ram          0x53440    stage        186664
+	    fallback/ramstage          0x53440    stage        186664
 	    fallback/payload               0x80dc0    payload      51526
 	    config                         0x8d740    raw          3324
 	    (empty)                        0x8e480    null         3610440
diff --git a/src/arch/aarch64/Makefile.inc b/src/arch/aarch64/Makefile.inc
index e2fe2cbeb5..a3cbec7dad 100644
--- a/src/arch/aarch64/Makefile.inc
+++ b/src/arch/aarch64/Makefile.inc
@@ -61,10 +61,10 @@ $(obj)/coreboot.pre: $(CBFSTOOL)
 	mv $(obj)/coreboot.rom $@
 endif
 
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE)
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 	cp $(obj)/coreboot.pre $@.tmp
-	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG)
+	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG)
 ifeq ($(CONFIG_PAYLOAD_NONE),y)
 	@printf "    PAYLOAD    none (as specified by user)\n"
 endif
@@ -105,17 +105,17 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
 	mv $@.tmp $@
 
 ################################################################################
-# Build the coreboot_ram (stage 2)
+# Build the ramstage (stage 2)
 
-$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/aarch64/coreboot_ram.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/aarch64/ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-	$(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/aarch64/coreboot_ram.ld
+	$(LD) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/aarch64/ramstage.ld
 else
-	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/aarch64/coreboot_ram.ld $<
+	$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/aarch64/ramstage.ld $<
 endif
 
-$(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME)
+$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
 	$(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group
diff --git a/src/arch/aarch64/coreboot_ram.ld b/src/arch/aarch64/ramstage.ld
similarity index 97%
rename from src/arch/aarch64/coreboot_ram.ld
rename to src/arch/aarch64/ramstage.ld
index 5345bfc98b..e878820352 100644
--- a/src/arch/aarch64/coreboot_ram.ld
+++ b/src/arch/aarch64/ramstage.ld
@@ -17,7 +17,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+ *  2005.12 yhlu add ramstage cross the vga font buffer handling
  */
 
 /* We use ELF as output format. So that we can debug the code in some form. */
diff --git a/src/arch/aarch64/romstage.ld b/src/arch/aarch64/romstage.ld
index 7ebe53f62a..029bd8bd2f 100644
--- a/src/arch/aarch64/romstage.ld
+++ b/src/arch/aarch64/romstage.ld
@@ -16,7 +16,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+ *  2005.12 yhlu add ramstage cross the vga font buffer handling
  */
 
 /* We use ELF as output format. So that we can debug the code in some form. */
diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc
index 5ca24b89c4..c62e879aa3 100644
--- a/src/arch/arm/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -132,10 +132,10 @@ $(obj)/coreboot.pre1: $(CBFSTOOL)
 	mv $(obj)/coreboot.rom $@
 endif
 
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(VBOOT_STUB)
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(VBOOT_STUB)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 	cp $(obj)/coreboot.pre $@.tmp
-	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG)
+	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG)
 ifeq ($(CONFIG_PAYLOAD_NONE),y)
 	@printf "    PAYLOAD    none (as specified by user)\n"
 endif
@@ -182,12 +182,12 @@ endif
 ################################################################################
 # Build the ramstage
 
-$(objcbfs)/coreboot_ram.debug: $$(ramstage-objs) $(src)/arch/arm/coreboot_ram.ld $(obj)/ldoptions
+$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-	$(LD) -nostdlib -m armelf_linux_eabi --gc-sections -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm/coreboot_ram.ld
+	$(LD) -nostdlib -m armelf_linux_eabi --gc-sections -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --start-group $(ramstage-objs) --end-group -T $(src)/arch/arm/ramstage.ld
 else
-	$(CC) $(CFLAGS) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) -Wl,--end-group -T $(src)/arch/arm/coreboot_ram.ld
+	$(CC) $(CFLAGS) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld
 endif
 
 ################################################################################
diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S
index e4d43029fe..ebd64a7425 100644
--- a/src/arch/arm/armv4/bootblock.S
+++ b/src/arch/arm/armv4/bootblock.S
@@ -84,6 +84,6 @@ ENDPROC(_start)
 .Stack:
 	.word CONFIG_STACK_TOP
 .align 2
-/* create this size the same way we do in coreboot_ram.ld: top-bottom */
+/* create this size the same way we do in ramstage.ld: top-bottom */
 .Stack_size:
 	.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM
diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
index 0439f2af81..3fdb1dd236 100644
--- a/src/arch/arm/armv7/bootblock.S
+++ b/src/arch/arm/armv7/bootblock.S
@@ -98,6 +98,6 @@ ENDPROC(_thumb_start)
 .Stack:
 	.word CONFIG_STACK_TOP
 .align 2
-/* create this size the same way we do in coreboot_ram.ld: top-bottom */
+/* create this size the same way we do in ramstage.ld: top-bottom */
 .Stack_size:
 	.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM
diff --git a/src/arch/arm/coreboot_ram.ld b/src/arch/arm/ramstage.ld
similarity index 97%
rename from src/arch/arm/coreboot_ram.ld
rename to src/arch/arm/ramstage.ld
index ba5200aa08..48f4e78eef 100644
--- a/src/arch/arm/coreboot_ram.ld
+++ b/src/arch/arm/ramstage.ld
@@ -16,7 +16,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+ *  2005.12 yhlu add ramstage cross the vga font buffer handling
  */
 
 /* We use ELF as output format. So that we can debug the code in some form. */
diff --git a/src/arch/arm/romstage.ld b/src/arch/arm/romstage.ld
index 22279aca93..17123ef0a4 100644
--- a/src/arch/arm/romstage.ld
+++ b/src/arch/arm/romstage.ld
@@ -16,7 +16,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+ *  2005.12 yhlu add ramstage cross the vga font buffer handling
  */
 
 /* We use ELF as output format. So that we can debug the code in some form. */
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 96a4e6ff86..c45d92db3d 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -80,10 +80,10 @@ $(REFCODE_BLOB): $(RMODTOOL)
 	$(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@
 endif
 
-$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB)
+$(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) $$(INTERMEDIATE) $$(VBOOT_STUB) $(REFCODE_BLOB)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
 	cp $(obj)/coreboot.pre $@.tmp
-	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG)
+	$(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/ramstage.elf -n $(CONFIG_CBFS_PREFIX)/ramstage -c $(CBFS_COMPRESS_FLAG)
 ifeq ($(CONFIG_PAYLOAD_NONE),y)
 	@printf "    PAYLOAD    none (as specified by user)\n"
 endif
@@ -170,29 +170,29 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug
 	mv $@.tmp $@
 
 ################################################################################
-# Build the coreboot_ram (stage 2)
+# Build the ramstage (stage 2)
 
 ifeq ($(CONFIG_RELOCATABLE_RAMSTAGE),y)
 
-$(eval $(call rmodule_link,$(objcbfs)/coreboot_ram.debug, $(objgenerated)/coreboot_ram.o, $(CONFIG_HEAP_SIZE)))
+$(eval $(call rmodule_link,$(objcbfs)/ramstage.debug, $(objgenerated)/ramstage.o, $(CONFIG_HEAP_SIZE)))
 
 # The rmodule_link defintion creates an elf file with .rmod extension.
-$(objcbfs)/coreboot_ram.elf: $(objcbfs)/coreboot_ram.debug.rmod
+$(objcbfs)/ramstage.elf: $(objcbfs)/ramstage.debug.rmod
 	cp $< $@
 
 else
 
-$(objcbfs)/coreboot_ram.debug: $(objgenerated)/coreboot_ram.o $(src)/arch/x86/coreboot_ram.ld
+$(objcbfs)/ramstage.debug: $(objgenerated)/ramstage.o $(src)/arch/x86/ramstage.ld
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-	$(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/coreboot_ram.ld
+	$(LD) -m elf_i386 -o $@ -L$(obj) $< -T $(src)/arch/x86/ramstage.ld
 else
-	$(CC) $(CFLAGS) -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/coreboot_ram.ld $<
+	$(CC) $(CFLAGS) -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/x86/ramstage.ld $<
 endif
 
 endif
 
-$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME)
+$(objgenerated)/ramstage.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
 	$(LD) -m elf_i386 -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group
diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index 6379842563..5a0b1fc9e6 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -42,5 +42,5 @@ static void cbfs_and_run_core(const char *filename)
 
 void asmlinkage copy_and_run(void)
 {
-	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram");
+	cbfs_and_run_core(CONFIG_CBFS_PREFIX "/ramstage");
 }
diff --git a/src/arch/x86/coreboot_ram.ld b/src/arch/x86/ramstage.ld
similarity index 97%
rename from src/arch/x86/coreboot_ram.ld
rename to src/arch/x86/ramstage.ld
index ea32837844..74d1b13d5c 100644
--- a/src/arch/x86/coreboot_ram.ld
+++ b/src/arch/x86/ramstage.ld
@@ -16,7 +16,7 @@
 /*
  *	Written by Johan Rydberg, based on work by Daniel Kahlin.
  *      Rewritten by Eric Biederman
- *  2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+ *  2005.12 yhlu add ramstage cross the vga font buffer handling
  */
 
 /* We use ELF as output format. So that we can debug the code in some form. */
diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
index 24533c7eb9..7776ae7224 100644
--- a/src/cpu/amd/car/disable_cache_as_ram.c
+++ b/src/cpu/amd/car/disable_cache_as_ram.c
@@ -36,7 +36,7 @@ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
 #if CONFIG_DCACHE_RAM_SIZE > 0x8000
 	wrmsr(MTRRfix4K_C0000_MSR, msr);
 #endif
-	/* disable fixed mtrr from now on, it will be enabled by coreboot_ram again*/
+	/* disable fixed mtrr from now on, it will be enabled by ramstage again*/
 
 	msr = rdmsr(SYSCFG_MSR);
 	msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn);
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 68e7c09ad3..eae1933878 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -164,7 +164,7 @@ static void post_cache_as_ram(void)
 
 	set_sysinfo_in_ram(1); // So other core0 could start to train mem
 
-	/*copy and execute coreboot_ram */
+	/*copy and execute ramstage */
 	copy_and_run();
 	/* We will not return */
 
diff --git a/src/cpu/amd/geode_lx/msrinit.c b/src/cpu/amd/geode_lx/msrinit.c
index 11182501c1..84fa548d59 100644
--- a/src/cpu/amd/geode_lx/msrinit.c
+++ b/src/cpu/amd/geode_lx/msrinit.c
@@ -42,11 +42,11 @@ static const msrinit_t msr_table[] =
 
 	/* Pre-setup access to memory above 1Mb. Here we set up about 500Mb of memory.
 	 * It doesn't really matter in fact how much, however, because the only usage
-	 * of this extended memory will be to host the coreboot_ram stage at RAMBASE,
+	 * of this extended memory will be to host the ramstage stage at RAMBASE,
 	 * currently 1Mb.
 	 * These registers will be set to their correct value by the Northbridge init code.
 	 *
-	 * WARNING: if coreboot_ram could not be loaded, these registers are probably
+	 * WARNING: if ramstage could not be loaded, these registers are probably
 	 * incorrectly set here. You may comment the following two lines and set RAMBASE
 	 * to 0x4000 to revert to the previous behavior for LX-boards.
 	 */
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index 2652cb7433..d147bd3a7d 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -248,7 +248,7 @@ before_romstage:
 	post_code(0x38)
 
 	/* Enable Write Back and Speculative Reads for the first MB
-	 * and coreboot_ram.
+	 * and ramstage.
 	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c
index 814c5f161f..935473828c 100644
--- a/src/cpu/x86/pae/pgtbl.c
+++ b/src/cpu/x86/pae/pgtbl.c
@@ -1,5 +1,5 @@
 /*
-	2005.12 yhlu add coreboot_ram cross the vga font buffer handling
+	2005.12 yhlu add ramstage cross the vga font buffer handling
 */
 
 #include <console/console.h>
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld
index 401f65fb3a..fded252fcb 100644
--- a/src/lib/rmodule.ld
+++ b/src/lib/rmodule.ld
@@ -34,7 +34,7 @@ SECTIONS
 
 		/* The driver sections are to allow linking coreboot's
 		 * ramstage with the rmodule linker. Any changes made in
-		 * coreboot_ram.ld should be made here as well. */
+		 * ramstage.ld should be made here as well. */
 		console_drivers = .;
 		*(.rodata.console_drivers)
 		econsole_drivers = . ;
diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c
index 4fc56d710b..7193b4b550 100644
--- a/src/lib/selfboot.c
+++ b/src/lib/selfboot.c
@@ -38,7 +38,7 @@
 #define MAX_ADDR -1UL
 #endif
 
-/* from coreboot_ram.ld: */
+/* from ramstage.ld: */
 extern unsigned char _ram_seg;
 extern unsigned char _eram_seg;
 
@@ -488,7 +488,7 @@ static int load_self_segments(
 				/* Zero the extra bytes */
 				memset(middle, 0, end - middle);
 			}
-			/* Copy the data that's outside the area that shadows coreboot_ram */
+			/* Copy the data that's outside the area that shadows ramstage */
 			printk(BIOS_DEBUG, "dest %p, end %p, bouncebuffer %lx\n", dest, end, bounce_buffer);
 			if ((unsigned long)end > bounce_buffer) {
 				if ((unsigned long)dest < bounce_buffer) {
diff --git a/src/mainboard/emulation/foundation-armv8/romstage.c b/src/mainboard/emulation/foundation-armv8/romstage.c
index 41026626f9..52e3cb1422 100644
--- a/src/mainboard/emulation/foundation-armv8/romstage.c
+++ b/src/mainboard/emulation/foundation-armv8/romstage.c
@@ -23,7 +23,7 @@ void main(void)
 
 	console_init();
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 
 	stage_exit(entry);
 }
diff --git a/src/mainboard/emulation/qemu-armv7/romstage.c b/src/mainboard/emulation/qemu-armv7/romstage.c
index 4a16436015..00dfecd431 100644
--- a/src/mainboard/emulation/qemu-armv7/romstage.c
+++ b/src/mainboard/emulation/qemu-armv7/romstage.c
@@ -23,7 +23,7 @@ void main(void)
 
 	console_init();
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 
 	stage_exit(entry);
 }
diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c
index 2fa5b298a8..f3975fbc41 100644
--- a/src/mainboard/google/daisy/romstage.c
+++ b/src/mainboard/google/daisy/romstage.c
@@ -196,7 +196,7 @@ void main(void)
 	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
 #endif
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 
 #if CONFIG_COLLECT_TIMESTAMPS
 	timestamp_add_now(TS_END_ROMSTAGE);
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index 4e023654e7..4f99e5435a 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -232,7 +232,7 @@ static void __attribute__((noinline)) romstage(void)
 
 	timestamp_add(TS_START_COPYRAM, timestamp_get());
 	void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
-				      "fallback/coreboot_ram");
+				      "fallback/ramstage");
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
 
 	stage_exit(entry);
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 4e023654e7..4f99e5435a 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -232,7 +232,7 @@ static void __attribute__((noinline)) romstage(void)
 
 	timestamp_add(TS_START_COPYRAM, timestamp_get());
 	void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
-				      "fallback/coreboot_ram");
+				      "fallback/ramstage");
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
 
 	stage_exit(entry);
diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c
index 4e023654e7..4f99e5435a 100644
--- a/src/mainboard/google/nyan_blaze/romstage.c
+++ b/src/mainboard/google/nyan_blaze/romstage.c
@@ -232,7 +232,7 @@ static void __attribute__((noinline)) romstage(void)
 
 	timestamp_add(TS_START_COPYRAM, timestamp_get());
 	void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
-				      "fallback/coreboot_ram");
+				      "fallback/ramstage");
 	timestamp_add(TS_END_COPYRAM, timestamp_get());
 
 	stage_exit(entry);
diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c
index 2553fdf0ed..0614b2c60b 100644
--- a/src/mainboard/google/peach_pit/romstage.c
+++ b/src/mainboard/google/peach_pit/romstage.c
@@ -292,7 +292,7 @@ void main(void)
 	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
 #endif
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 	simple_spi_test();
 
 #if CONFIG_COLLECT_TIMESTAMPS
diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c
index cf78e44225..856718cf19 100644
--- a/src/mainboard/google/storm/romstage.c
+++ b/src/mainboard/google/storm/romstage.c
@@ -25,6 +25,6 @@ void main(void)
 {
 	void *entry;
 
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage");
 	stage_exit(entry);
 }
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index eded51555a..c6ec572024 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1033,7 +1033,7 @@ struct nodes_info_t {
 	u32 up_planes; // down planes will be [up_planes, planes)
 } __attribute__((packed));
 
-/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and coreboot_ram stage. and coreboot_ram may be running at 64bit later.*/
+/* be careful with the alignment of sysinfo, bacause sysinfo may be shared by coreboot_car and ramstage stage. and ramstage may be running at 64bit later.*/
 #if !CONFIG_AMDMCT
 
 //#define MEM_CS_COPY 1
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index e5bcdcb9c1..a4943bd2b9 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -80,7 +80,7 @@ unsigned node_link_to_bus(unsigned node, unsigned link)
  *     pci1234[0] will record the south bridge link and bus range
  *     pci1234[i] will record HT chain i.
  *
- * For example, on the Tyan S2885 coreboot_ram will put the AMD8151 chain (HT
+ * For example, on the Tyan S2885 ramstage will put the AMD8151 chain (HT
  * link 0) into the register 0xE0, and the AMD8131/8111 HT chain into the
  * register 0xE4.
  *
diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S
index e4d43029fe..ebd64a7425 100644
--- a/src/soc/nvidia/tegra124/bootblock_asm.S
+++ b/src/soc/nvidia/tegra124/bootblock_asm.S
@@ -84,6 +84,6 @@ ENDPROC(_start)
 .Stack:
 	.word CONFIG_STACK_TOP
 .align 2
-/* create this size the same way we do in coreboot_ram.ld: top-bottom */
+/* create this size the same way we do in ramstage.ld: top-bottom */
 .Stack_size:
 	.word CONFIG_STACK_TOP - CONFIG_STACK_BOTTOM
diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c
index 60f7abbc5f..9dee295c0d 100644
--- a/src/southbridge/broadcom/bcm5785/early_setup.c
+++ b/src/southbridge/broadcom/bcm5785/early_setup.c
@@ -177,7 +177,7 @@ static void bcm5785_early_setup(void)
         byte |= (1<<0); // SATA enable
         pci_write_config8(dev, 0x84, byte);
 
-// WDT and cf9 for later in coreboot_ram to call hard_reset
+// WDT and cf9 for later in ramstage to call hard_reset
         bcm5785_enable_wdt_port_cf9();
 
         bcm5785_enable_msg();
diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c
index 52b4b3ec4f..8721bf19a6 100644
--- a/src/vendorcode/google/chromeos/vboot_loader.c
+++ b/src/vendorcode/google/chromeos/vboot_loader.c
@@ -314,7 +314,7 @@ static void vboot_load_ramstage(struct vboot_handoff *vboot_handoff,
 	const struct firmware_component *fwc;
 	struct rmod_stage_load rmod_load = {
 		.cbmem_id = CBMEM_ID_RAMSTAGE,
-		.name = CONFIG_CBFS_PREFIX "/coreboot_ram",
+		.name = CONFIG_CBFS_PREFIX "/ramstage",
 	};
 
 	if (CONFIG_VBOOT_RAMSTAGE_INDEX >= MAX_PARSED_FW_COMPONENTS) {
diff --git a/util/genprof/README b/util/genprof/README
index fc14849072..d4159c2fd6 100644
--- a/util/genprof/README
+++ b/util/genprof/README
@@ -26,6 +26,6 @@ that.
 Great use is:
 
 make
-./genprof /tmp/yourlog ;  gprof ../../build/coreboot_ram |  ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png
+./genprof /tmp/yourlog ;  gprof ../../build/ramstage |  ./gprof2dot.py -e0 -n0 | dot -Tpng -o output.png
 
 Which generates a PNG with a call graph.
diff --git a/util/genprof/log2dress b/util/genprof/log2dress
index c901a81d78..99d1f2f59c 100755
--- a/util/genprof/log2dress
+++ b/util/genprof/log2dress
@@ -10,9 +10,9 @@ A=`echo $line | cut -c 1`
 if [ "$A" = '~' ] ; then
 FROM=`echo $line | tr \~ \( | tr \) \(  | awk -F\( '{print $3}'`
 TO=`echo $line  | tr \~ \( | tr \) \(|awk -F\( '{print $2}'`
-addr2line -e ../../build/cbfs/fallback/coreboot_ram.debug "$FROM" | tr -d "\n"
+addr2line -e ../../build/cbfs/fallback/ramstage.debug "$FROM" | tr -d "\n"
 echo -n " calls "
-addr2line -e ../../build/cbfs/fallback/coreboot_ram.debug "$TO"
+addr2line -e ../../build/cbfs/fallback/ramstage.debug "$TO"
 else
 echo "$line"
 fi