From d740cee2d9bd25c7d6f003e4b611218f0f37d5dd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 23 Feb 2026 21:17:38 +0100 Subject: [PATCH] soc/intel/broadwell/pch: Move to sb/intel/wildcatpoint The PCH split was done many moons ago, in order to unify two codebases with overlapping hardware support: Haswell + Lynx Point and Broadwell. The on-package PCH found in Broadwell ULT/ULX CPUs is Wildcat Point. This change only moves the files, and does the minimal amount of edits so that boards still build. Most of those edits boil down to "find and replace". Change-Id: I29235b47970f81b5db6717801f2ab771ff980476 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/91396 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/devicetree.cb | 2 +- src/mainboard/google/auron/dsdt.asl | 4 +- .../variants/auron_paine/overridetree.cb | 2 +- .../auron/variants/auron_yuna/overridetree.cb | 2 +- .../auron/variants/buddy/overridetree.cb | 2 +- .../auron/variants/gandof/overridetree.cb | 2 +- .../auron/variants/lulu/overridetree.cb | 2 +- .../auron/variants/samus/overridetree.cb | 2 +- src/mainboard/google/jecht/devicetree.cb | 2 +- src/mainboard/google/jecht/dsdt.asl | 4 +- .../hp/elitebook_820_g2/devicetree.cb | 2 +- src/mainboard/hp/elitebook_820_g2/dsdt.asl | 4 +- src/mainboard/intel/wtm2/devicetree.cb | 2 +- src/mainboard/intel/wtm2/dsdt.asl | 4 +- src/mainboard/purism/librem_bdw/devicetree.cb | 2 +- src/mainboard/purism/librem_bdw/dsdt.asl | 4 +- .../variants/librem13v1/overridetree.cb | 2 +- .../variants/librem15v2/overridetree.cb | 2 +- src/soc/intel/broadwell/Kconfig | 4 +- src/soc/intel/broadwell/pch/Makefile.mk | 45 ----------------- .../intel/wildcatpoint}/Kconfig | 11 +++- .../intel/wildcatpoint/Makefile.mk | 50 +++++++++++++++++++ .../intel/wildcatpoint}/acpi/adsp.asl | 0 .../intel/wildcatpoint}/acpi/globalnvs.asl | 0 .../intel/wildcatpoint}/acpi/gpio.asl | 0 .../intel/wildcatpoint}/acpi/lpc.asl | 0 .../intel/wildcatpoint}/acpi/pch.asl | 0 .../intel/wildcatpoint}/acpi/pci_irqs.asl | 0 .../intel/wildcatpoint}/acpi/serialio.asl | 0 .../intel/wildcatpoint}/acpi/xhci.asl | 0 .../intel/wildcatpoint}/adsp.c | 4 +- .../intel/wildcatpoint}/bootblock.c | 0 .../intel/wildcatpoint}/chip.h | 2 +- .../intel/wildcatpoint}/early_pch.c | 4 +- .../intel/wildcatpoint}/elog.c | 0 .../intel/wildcatpoint}/fadt.c | 0 .../intel/wildcatpoint}/finalize.c | 0 .../intel/wildcatpoint}/hda.c | 0 .../intel/wildcatpoint}/lpc.c | 8 +-- .../intel/wildcatpoint}/me.c | 4 +- .../intel/wildcatpoint}/me_status.c | 0 .../intel/wildcatpoint}/pch.c | 2 +- .../intel/wildcatpoint}/pcie.c | 6 +-- .../intel/wildcatpoint}/pmutil.c | 0 .../intel/wildcatpoint}/power_state.c | 0 .../intel/wildcatpoint}/ramstage.c | 0 .../intel/wildcatpoint}/sata.c | 6 +-- .../intel/wildcatpoint}/serialio.c | 4 +- .../intel/wildcatpoint}/smi.c | 0 .../intel/wildcatpoint}/smihandler.c | 0 .../intel/wildcatpoint}/usb_debug.c | 0 .../intel/wildcatpoint}/usb_ehci.c | 0 .../intel/wildcatpoint}/usb_xhci.c | 0 53 files changed, 104 insertions(+), 92 deletions(-) delete mode 100644 src/soc/intel/broadwell/pch/Makefile.mk rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/Kconfig (93%) create mode 100644 src/southbridge/intel/wildcatpoint/Makefile.mk rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/adsp.asl (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/globalnvs.asl (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/gpio.asl (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/lpc.asl (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/pch.asl (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/pci_irqs.asl (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/serialio.asl (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/acpi/xhci.asl (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/adsp.c (96%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/bootblock.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/chip.h (97%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/early_pch.c (95%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/elog.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/fadt.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/finalize.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/hda.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/lpc.c (98%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/me.c (99%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/me_status.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/pch.c (98%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/pcie.c (98%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/pmutil.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/power_state.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/ramstage.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/sata.c (97%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/serialio.c (98%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/smi.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/smihandler.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/usb_debug.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/usb_ehci.c (100%) rename src/{soc/intel/broadwell/pch => southbridge/intel/wildcatpoint}/usb_xhci.c (100%) diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 6d42e1f810..ff179c2ceb 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -26,7 +26,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint # EC range is 0x800-0x9ff register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" diff --git a/src/mainboard/google/auron/dsdt.asl b/src/mainboard/google/auron/dsdt.asl index ba7f1e4324..c6453e9a24 100644 --- a/src/mainboard/google/auron/dsdt.asl +++ b/src/mainboard/google/auron/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include "acpi/thermal.asl" // global NVS and variables - #include + #include // CPU #include @@ -26,7 +26,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include #include } } diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 62e42b1718..b968ddb6bd 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/broadwell }" device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 174463d0b7..c9d9078c46 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/broadwell }" device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x7" register "sata_port1_gen3_dtle" = "0x5" diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index d1e217b8aa..e1bf686cc8 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -18,7 +18,7 @@ chip soc/intel/broadwell end device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint register "sata_devslp_disable" = "0x1" register "sio_i2c0_voltage" = "1" # 1.8V diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index ca5d616659..ddb7a35dfa 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/broadwell }" device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 62e42b1718..b968ddb6bd 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -10,7 +10,7 @@ chip soc/intel/broadwell }" device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index b0b8a603f6..b9a6431d0e 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -26,7 +26,7 @@ chip soc/intel/broadwell end device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint register "sata_port0_gen3_tx" = "0x72" # Set I2C0 to 1.8V diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index cdde70f503..2f8ccdc365 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -21,7 +21,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" diff --git a/src/mainboard/google/jecht/dsdt.asl b/src/mainboard/google/jecht/dsdt.asl index 1aeb08cdce..7cc8c7b9f4 100644 --- a/src/mainboard/google/jecht/dsdt.asl +++ b/src/mainboard/google/jecht/dsdt.asl @@ -18,7 +18,7 @@ DefinitionBlock( #include // global NVS and variables - #include + #include #include // CPU @@ -28,7 +28,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include } } diff --git a/src/mainboard/hp/elitebook_820_g2/devicetree.cb b/src/mainboard/hp/elitebook_820_g2/devicetree.cb index 626e6d56a7..63df5d16d9 100644 --- a/src/mainboard/hp/elitebook_820_g2/devicetree.cb +++ b/src/mainboard/hp/elitebook_820_g2/devicetree.cb @@ -24,7 +24,7 @@ chip soc/intel/broadwell end device pci 03.0 on end # Mini-HD audio - chip soc/intel/broadwell/pch # Wildcat Point PCH + chip southbridge/intel/wildcatpoint # Wildcat Point PCH device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # xHCI Controller device pci 15.0 off end # Serial I/O DMA diff --git a/src/mainboard/hp/elitebook_820_g2/dsdt.asl b/src/mainboard/hp/elitebook_820_g2/dsdt.asl index 6d7555d02e..6b1b4267d5 100644 --- a/src/mainboard/hp/elitebook_820_g2/dsdt.asl +++ b/src/mainboard/hp/elitebook_820_g2/dsdt.asl @@ -17,7 +17,7 @@ DefinitionBlock( #include "acpi/platform.asl" #include - #include + #include #include #include #include @@ -25,7 +25,7 @@ DefinitionBlock( Device (\_SB.PCI0) { #include - #include + #include #include } } diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 9e1e8a03cb..0b8bd36085 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -18,7 +18,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000400" register "gpe0_en_2" = "0x00000000" diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 9e06eb7202..26ed596067 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -18,7 +18,7 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include + #include #include // CPU @@ -28,7 +28,7 @@ DefinitionBlock( Device (PCI0) { #include - #include + #include } } diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index f663afdd4c..934fd7eb8b 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -29,7 +29,7 @@ chip soc/intel/broadwell device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" diff --git a/src/mainboard/purism/librem_bdw/dsdt.asl b/src/mainboard/purism/librem_bdw/dsdt.asl index a631e5a5a5..2e8b5c57e2 100644 --- a/src/mainboard/purism/librem_bdw/dsdt.asl +++ b/src/mainboard/purism/librem_bdw/dsdt.asl @@ -12,14 +12,14 @@ DefinitionBlock( { #include #include - #include + #include #include Scope (\_SB) { Device (PCI0) { #include - #include + #include #include } } diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index 256077cbd9..9d47ae8055 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index 76737cc5e2..01d317e6b5 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -3,7 +3,7 @@ chip soc/intel/broadwell register "dq_pins_interleaved" = "true" device domain 0 on - chip soc/intel/broadwell/pch + chip southbridge/intel/wildcatpoint # Port 0 is HDD # Port 1 is M.2 NGFF register "sata_port_map" = "0x3" diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 74650ff212..e20ac3f1d7 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -10,7 +10,7 @@ config SOC_INTEL_BROADWELL select MRC_SETTINGS_PROTECT select REG_SCRIPT select TCO_SPACE_NOT_YET_SPLIT - select INTEL_LYNXPOINT_LP + select SOUTHBRIDGE_INTEL_WILDCATPOINT help Intel Broadwell and Haswell ULT support. @@ -117,6 +117,4 @@ config REFCODE_BLOB_FILE endif # HAVE_REFCODE_BLOB -source "src/soc/intel/broadwell/pch/Kconfig" - endif diff --git a/src/soc/intel/broadwell/pch/Makefile.mk b/src/soc/intel/broadwell/pch/Makefile.mk deleted file mode 100644 index be2f4a4292..0000000000 --- a/src/soc/intel/broadwell/pch/Makefile.mk +++ /dev/null @@ -1,45 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += bootblock.c - -ramstage-y += adsp.c -romstage-y += early_pch.c -ramstage-$(CONFIG_ELOG) += elog.c -ramstage-y += finalize.c -ramstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c -romstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c -verstage-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c -smm-y += ../../../../southbridge/intel/lynxpoint/lp_gpio.c -ramstage-y += hda.c -ramstage-y += ../../../../southbridge/intel/lynxpoint/hda_verb.c -ramstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c -romstage-y += ../../../../southbridge/intel/lynxpoint/iobp.c -ramstage-y += fadt.c -ramstage-y += lpc.c -ramstage-y += me.c -ramstage-y += me_status.c -romstage-y += me_status.c -ramstage-y += pch.c -romstage-y += pch.c -ramstage-y += pcie.c -ramstage-y += pmutil.c -romstage-y += pmutil.c -smm-y += pmutil.c -verstage-y += pmutil.c -romstage-y += power_state.c -ramstage-y += ramstage.c -ramstage-y += sata.c -ramstage-y += serialio.c -ramstage-y += ../../../../southbridge/intel/lynxpoint/smbus.c -ramstage-y += smi.c -smm-y += smihandler.c -bootblock-y += usb_debug.c -romstage-y += usb_debug.c -ramstage-y += usb_debug.c -ramstage-y += usb_ehci.c -ramstage-y += usb_xhci.c -smm-y += usb_xhci.c - -bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/iobp.c -bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/uart_init.c -all-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/uart.c -smm-$(CONFIG_SERIALIO_UART_CONSOLE) += ../../../../southbridge/intel/lynxpoint/uart.c diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/southbridge/intel/wildcatpoint/Kconfig similarity index 93% rename from src/soc/intel/broadwell/pch/Kconfig rename to src/southbridge/intel/wildcatpoint/Kconfig index a671207b67..424b91d832 100644 --- a/src/soc/intel/broadwell/pch/Kconfig +++ b/src/southbridge/intel/wildcatpoint/Kconfig @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -config INTEL_LYNXPOINT_LP +config SOUTHBRIDGE_INTEL_WILDCATPOINT bool select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC @@ -14,6 +14,7 @@ config INTEL_LYNXPOINT_LP select HAVE_SMI_HANDLER select HAVE_USBDEBUG select INTEL_DESCRIPTOR_MODE_CAPABLE + select INTEL_LYNXPOINT_LP select RTC select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS select SOUTHBRIDGE_INTEL_COMMON_RESET @@ -23,6 +24,12 @@ config INTEL_LYNXPOINT_LP select SPI_FLASH select TCO_SPACE_NOT_YET_SPLIT +if SOUTHBRIDGE_INTEL_WILDCATPOINT + +# Placeholder +config INTEL_LYNXPOINT_LP + bool + config EHCI_BAR hex default 0xd8000000 @@ -72,3 +79,5 @@ config DISABLE_ME_PCI Disable and hide the ME PCI interface during finalize stage of boot. This will prevent the OS (and userspace apps) from interacting with the ME via the PCI interface after boot. + +endif diff --git a/src/southbridge/intel/wildcatpoint/Makefile.mk b/src/southbridge/intel/wildcatpoint/Makefile.mk new file mode 100644 index 0000000000..ee631d44cd --- /dev/null +++ b/src/southbridge/intel/wildcatpoint/Makefile.mk @@ -0,0 +1,50 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_WILDCATPOINT),y) + +bootblock-y += bootblock.c + +ramstage-y += adsp.c +romstage-y += early_pch.c +ramstage-$(CONFIG_ELOG) += elog.c +ramstage-y += finalize.c +ramstage-y += ../lynxpoint/lp_gpio.c +romstage-y += ../lynxpoint/lp_gpio.c +verstage-y += ../lynxpoint/lp_gpio.c +smm-y += ../lynxpoint/lp_gpio.c +ramstage-y += hda.c +ramstage-y += ../lynxpoint/hda_verb.c +ramstage-y += ../lynxpoint/iobp.c +romstage-y += ../lynxpoint/iobp.c +ramstage-y += fadt.c +ramstage-y += lpc.c +ramstage-y += me.c +ramstage-y += me_status.c +romstage-y += me_status.c +ramstage-y += pch.c +romstage-y += pch.c +ramstage-y += pcie.c +ramstage-y += pmutil.c +romstage-y += pmutil.c +smm-y += pmutil.c +verstage-y += pmutil.c +romstage-y += power_state.c +ramstage-y += ramstage.c +ramstage-y += sata.c +ramstage-y += serialio.c +ramstage-y += ../lynxpoint/smbus.c +ramstage-y += smi.c +smm-y += smihandler.c +bootblock-y += usb_debug.c +romstage-y += usb_debug.c +ramstage-y += usb_debug.c +ramstage-y += usb_ehci.c +ramstage-y += usb_xhci.c +smm-y += usb_xhci.c + +bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/iobp.c +bootblock-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart_init.c +all-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart.c +smm-$(CONFIG_SERIALIO_UART_CONSOLE) += ../lynxpoint/uart.c + +endif diff --git a/src/soc/intel/broadwell/pch/acpi/adsp.asl b/src/southbridge/intel/wildcatpoint/acpi/adsp.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/adsp.asl rename to src/southbridge/intel/wildcatpoint/acpi/adsp.asl diff --git a/src/soc/intel/broadwell/pch/acpi/globalnvs.asl b/src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/globalnvs.asl rename to src/southbridge/intel/wildcatpoint/acpi/globalnvs.asl diff --git a/src/soc/intel/broadwell/pch/acpi/gpio.asl b/src/southbridge/intel/wildcatpoint/acpi/gpio.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/gpio.asl rename to src/southbridge/intel/wildcatpoint/acpi/gpio.asl diff --git a/src/soc/intel/broadwell/pch/acpi/lpc.asl b/src/southbridge/intel/wildcatpoint/acpi/lpc.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/lpc.asl rename to src/southbridge/intel/wildcatpoint/acpi/lpc.asl diff --git a/src/soc/intel/broadwell/pch/acpi/pch.asl b/src/southbridge/intel/wildcatpoint/acpi/pch.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/pch.asl rename to src/southbridge/intel/wildcatpoint/acpi/pch.asl diff --git a/src/soc/intel/broadwell/pch/acpi/pci_irqs.asl b/src/southbridge/intel/wildcatpoint/acpi/pci_irqs.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/pci_irqs.asl rename to src/southbridge/intel/wildcatpoint/acpi/pci_irqs.asl diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/southbridge/intel/wildcatpoint/acpi/serialio.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/serialio.asl rename to src/southbridge/intel/wildcatpoint/acpi/serialio.asl diff --git a/src/soc/intel/broadwell/pch/acpi/xhci.asl b/src/southbridge/intel/wildcatpoint/acpi/xhci.asl similarity index 100% rename from src/soc/intel/broadwell/pch/acpi/xhci.asl rename to src/southbridge/intel/wildcatpoint/acpi/xhci.asl diff --git a/src/soc/intel/broadwell/pch/adsp.c b/src/southbridge/intel/wildcatpoint/adsp.c similarity index 96% rename from src/soc/intel/broadwell/pch/adsp.c rename to src/southbridge/intel/wildcatpoint/adsp.c index 05b1e60af2..c56f9cc584 100644 --- a/src/soc/intel/broadwell/pch/adsp.c +++ b/src/southbridge/intel/wildcatpoint/adsp.c @@ -11,13 +11,13 @@ #include #include #include -#include +#include #include #include static void adsp_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32; diff --git a/src/soc/intel/broadwell/pch/bootblock.c b/src/southbridge/intel/wildcatpoint/bootblock.c similarity index 100% rename from src/soc/intel/broadwell/pch/bootblock.c rename to src/southbridge/intel/wildcatpoint/bootblock.c diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/southbridge/intel/wildcatpoint/chip.h similarity index 97% rename from src/soc/intel/broadwell/pch/chip.h rename to src/southbridge/intel/wildcatpoint/chip.h index 84ad8fe820..dd31645849 100644 --- a/src/soc/intel/broadwell/pch/chip.h +++ b/src/southbridge/intel/wildcatpoint/chip.h @@ -5,7 +5,7 @@ #include -struct soc_intel_broadwell_pch_config { +struct southbridge_intel_wildcatpoint_config { /* GPE configuration */ uint32_t gpe0_en_1; uint32_t gpe0_en_2; diff --git a/src/soc/intel/broadwell/pch/early_pch.c b/src/southbridge/intel/wildcatpoint/early_pch.c similarity index 95% rename from src/soc/intel/broadwell/pch/early_pch.c rename to src/southbridge/intel/wildcatpoint/early_pch.c index cb45971772..adb65e6145 100644 --- a/src/soc/intel/broadwell/pch/early_pch.c +++ b/src/southbridge/intel/wildcatpoint/early_pch.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include static void pch_route_interrupts(void) { @@ -56,7 +56,7 @@ static void pch_enable_lpc(void) if (!dev || !dev->chip_info) return; - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info; pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/pch/elog.c b/src/southbridge/intel/wildcatpoint/elog.c similarity index 100% rename from src/soc/intel/broadwell/pch/elog.c rename to src/southbridge/intel/wildcatpoint/elog.c diff --git a/src/soc/intel/broadwell/pch/fadt.c b/src/southbridge/intel/wildcatpoint/fadt.c similarity index 100% rename from src/soc/intel/broadwell/pch/fadt.c rename to src/southbridge/intel/wildcatpoint/fadt.c diff --git a/src/soc/intel/broadwell/pch/finalize.c b/src/southbridge/intel/wildcatpoint/finalize.c similarity index 100% rename from src/soc/intel/broadwell/pch/finalize.c rename to src/southbridge/intel/wildcatpoint/finalize.c diff --git a/src/soc/intel/broadwell/pch/hda.c b/src/southbridge/intel/wildcatpoint/hda.c similarity index 100% rename from src/soc/intel/broadwell/pch/hda.c rename to src/southbridge/intel/wildcatpoint/hda.c diff --git a/src/soc/intel/broadwell/pch/lpc.c b/src/southbridge/intel/wildcatpoint/lpc.c similarity index 98% rename from src/soc/intel/broadwell/pch/lpc.c rename to src/southbridge/intel/wildcatpoint/lpc.c index 49a36b148a..9dd2350c93 100644 --- a/src/soc/intel/broadwell/pch/lpc.c +++ b/src/southbridge/intel/wildcatpoint/lpc.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include @@ -162,7 +162,7 @@ static void pch_power_options(struct device *dev) printk(BIOS_INFO, "Set power %s after power failure.\n", state); if (dev->chip_info) { - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info; /* GPE setup based on device tree configuration */ enable_all_gpe(config->gpe0_en_1, config->gpe0_en_2, @@ -326,7 +326,7 @@ static void pch_enable_mphy(void) static void pch_init_deep_sx(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info; if (!config) return; @@ -575,7 +575,7 @@ static void pch_lpc_add_io_resources(struct device *dev) /* LPC Generic IO Decode range. */ if (dev->chip_info) { - const struct soc_intel_broadwell_pch_config *config = dev->chip_info; + const struct southbridge_intel_wildcatpoint_config *config = dev->chip_info; pch_lpc_add_gen_io_resources(dev, config->gen1_dec, LPC_GEN1_DEC); pch_lpc_add_gen_io_resources(dev, config->gen2_dec, LPC_GEN2_DEC); pch_lpc_add_gen_io_resources(dev, config->gen3_dec, LPC_GEN3_DEC); diff --git a/src/soc/intel/broadwell/pch/me.c b/src/southbridge/intel/wildcatpoint/me.c similarity index 99% rename from src/soc/intel/broadwell/pch/me.c rename to src/southbridge/intel/wildcatpoint/me.c index 5756bdb00d..33bf915fae 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/southbridge/intel/wildcatpoint/me.c @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include @@ -948,7 +948,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev) /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; int mbp_ret; diff --git a/src/soc/intel/broadwell/pch/me_status.c b/src/southbridge/intel/wildcatpoint/me_status.c similarity index 100% rename from src/soc/intel/broadwell/pch/me_status.c rename to src/southbridge/intel/wildcatpoint/me_status.c diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/southbridge/intel/wildcatpoint/pch.c similarity index 98% rename from src/soc/intel/broadwell/pch/pch.c rename to src/southbridge/intel/wildcatpoint/pch.c index fa03d7359a..3714a7d8a7 100644 --- a/src/soc/intel/broadwell/pch/pch.c +++ b/src/southbridge/intel/wildcatpoint/pch.c @@ -196,7 +196,7 @@ static void broadwell_pch_enable_dev(struct device *dev) } } -struct chip_operations soc_intel_broadwell_pch_ops = { +struct chip_operations southbridge_intel_wildcatpoint_ops = { .name = "Intel Broadwell PCH", .enable_dev = &broadwell_pch_enable_dev, }; diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/southbridge/intel/wildcatpoint/pcie.c similarity index 98% rename from src/soc/intel/broadwell/pch/pcie.c rename to src/southbridge/intel/wildcatpoint/pcie.c index 4847da6788..9262d3c628 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/southbridge/intel/wildcatpoint/pcie.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include @@ -121,7 +121,7 @@ static void root_port_init_config(struct device *dev) root_port_config_update_gbe_port(); pci_or_config8(dev, 0xe2, 3 << 4); - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); rpc.coalesce = config->pcie_port_coalesce; } @@ -435,7 +435,7 @@ static void pcie_add_0x0202000_iobp(u32 reg) static void pch_pcie_early(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev); diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/southbridge/intel/wildcatpoint/pmutil.c similarity index 100% rename from src/soc/intel/broadwell/pch/pmutil.c rename to src/southbridge/intel/wildcatpoint/pmutil.c diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/southbridge/intel/wildcatpoint/power_state.c similarity index 100% rename from src/soc/intel/broadwell/pch/power_state.c rename to src/southbridge/intel/wildcatpoint/power_state.c diff --git a/src/soc/intel/broadwell/pch/ramstage.c b/src/southbridge/intel/wildcatpoint/ramstage.c similarity index 100% rename from src/soc/intel/broadwell/pch/ramstage.c rename to src/southbridge/intel/wildcatpoint/ramstage.c diff --git a/src/soc/intel/broadwell/pch/sata.c b/src/southbridge/intel/wildcatpoint/sata.c similarity index 97% rename from src/soc/intel/broadwell/pch/sata.c rename to src/southbridge/intel/wildcatpoint/sata.c index 92d34c302c..d2bb5d37a1 100644 --- a/src/soc/intel/broadwell/pch/sata.c +++ b/src/southbridge/intel/wildcatpoint/sata.c @@ -9,7 +9,7 @@ #include #include #include -#include +#include #include static inline u32 sir_read(struct device *dev, int idx) @@ -26,7 +26,7 @@ static inline void sir_write(struct device *dev, int idx, u32 value) static void sata_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); u32 reg32; u8 *abar; u16 reg16; @@ -259,7 +259,7 @@ static void sata_init(struct device *dev) static void sata_enable(struct device *dev) { /* Get the chip configuration */ - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); u16 map = 0x0060; map |= (config->sata_port_map ^ 0xf) << 8; diff --git a/src/soc/intel/broadwell/pch/serialio.c b/src/southbridge/intel/wildcatpoint/serialio.c similarity index 98% rename from src/soc/intel/broadwell/pch/serialio.c rename to src/southbridge/intel/wildcatpoint/serialio.c index 336b501b32..bc86db3098 100644 --- a/src/soc/intel/broadwell/pch/serialio.c +++ b/src/southbridge/intel/wildcatpoint/serialio.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include @@ -156,7 +156,7 @@ static void serialio_init_once(int acpi_mode) static void serialio_init(struct device *dev) { - const struct soc_intel_broadwell_pch_config *config = config_of(dev); + const struct southbridge_intel_wildcatpoint_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1; diff --git a/src/soc/intel/broadwell/pch/smi.c b/src/southbridge/intel/wildcatpoint/smi.c similarity index 100% rename from src/soc/intel/broadwell/pch/smi.c rename to src/southbridge/intel/wildcatpoint/smi.c diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/southbridge/intel/wildcatpoint/smihandler.c similarity index 100% rename from src/soc/intel/broadwell/pch/smihandler.c rename to src/southbridge/intel/wildcatpoint/smihandler.c diff --git a/src/soc/intel/broadwell/pch/usb_debug.c b/src/southbridge/intel/wildcatpoint/usb_debug.c similarity index 100% rename from src/soc/intel/broadwell/pch/usb_debug.c rename to src/southbridge/intel/wildcatpoint/usb_debug.c diff --git a/src/soc/intel/broadwell/pch/usb_ehci.c b/src/southbridge/intel/wildcatpoint/usb_ehci.c similarity index 100% rename from src/soc/intel/broadwell/pch/usb_ehci.c rename to src/southbridge/intel/wildcatpoint/usb_ehci.c diff --git a/src/soc/intel/broadwell/pch/usb_xhci.c b/src/southbridge/intel/wildcatpoint/usb_xhci.c similarity index 100% rename from src/soc/intel/broadwell/pch/usb_xhci.c rename to src/southbridge/intel/wildcatpoint/usb_xhci.c