diff --git a/src/mainboard/hp/260_g1_dm/Kconfig b/src/mainboard/hp/260_g1_dm/Kconfig new file mode 100644 index 0000000000..deae64a5a4 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/Kconfig @@ -0,0 +1,29 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_HP_260_G1_DM + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select CPU_INTEL_HASWELL + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select INTEL_LYNXPOINT_LP + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_TPM1 + select MEMORY_MAPPED_TPM + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NPCD378 + +config MAINBOARD_DIR + default "hp/260_g1_dm" + +config MAINBOARD_PART_NUMBER + default "260 G1 DM" + +config USBDEBUG_HCD_INDEX + default 1 +endif diff --git a/src/mainboard/hp/260_g1_dm/Kconfig.name b/src/mainboard/hp/260_g1_dm/Kconfig.name new file mode 100644 index 0000000000..2eccbf75c8 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_HP_260_G1_DM + bool "260 G1 DM" diff --git a/src/mainboard/hp/260_g1_dm/Makefile.mk b/src/mainboard/hp/260_g1_dm/Makefile.mk new file mode 100644 index 0000000000..c9500cfe9b --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/hp/260_g1_dm/acpi/ec.asl b/src/mainboard/hp/260_g1_dm/acpi/ec.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/hp/260_g1_dm/acpi/platform.asl b/src/mainboard/hp/260_g1_dm/acpi/platform.asl new file mode 100644 index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/hp/260_g1_dm/acpi/superio.asl b/src/mainboard/hp/260_g1_dm/acpi/superio.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/hp/260_g1_dm/board_info.txt b/src/mainboard/hp/260_g1_dm/board_info.txt new file mode 100644 index 0000000000..1c9a30d23a --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/board_info.txt @@ -0,0 +1,8 @@ +Category: desktop +Board URL: https://support.hp.com/us-en/product/setup-user-guides/hp-260-g1-desktop-mini-pc/7375834 +ROM IC: MX25L6406E +ROM protocol: SPI +Flashrom support: y +ROM package: SOIC8 +ROM socketed: no +Release year: 2015 diff --git a/src/mainboard/hp/260_g1_dm/data.vbt b/src/mainboard/hp/260_g1_dm/data.vbt new file mode 100644 index 0000000000..d89e108323 Binary files /dev/null and b/src/mainboard/hp/260_g1_dm/data.vbt differ diff --git a/src/mainboard/hp/260_g1_dm/devicetree.cb b/src/mainboard/hp/260_g1_dm/devicetree.cb new file mode 100644 index 0000000000..cf6c95bc35 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/devicetree.cb @@ -0,0 +1,160 @@ +chip northbridge/intel/haswell + register "dq_pins_interleaved" = "1" + register "ec_present" = "false" + + register "gpu_ddi_e_connected" = "1" + + register "spd_addresses" = "{0x50, 0, 0x51, 0}" + + chip cpu/intel/haswell + device cpu_cluster 0x0 on ops haswell_cpu_bus_ops end + end + device domain 0x0 on + ops haswell_pci_domain_ops + subsystemid 0x103c 0x8000 inherit + + device pci 00.0 on end # ULT Host bridge + device pci 02.0 on end # Internal graphics VGA controller + device pci 03.0 on end # Mini-HD audio + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "1" + register "gen1_dec" = "0x00fc0a01" + register "gen2_dec" = "0x00fc0b01" + register "gpe0_en_4" = "0x2046" + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x9" + register "sata_port_map" = "0x1" + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # xHCI Controller + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # Onboard Realtek LAN + device pci 1c.3 on end # X1PCIEXP11 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on # LPC bridge + chip superio/common + device pnp 2e.ff on # passes SIO base addr to SSDT gen + chip superio/nuvoton/npcd378 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off # Parallel port + # global + + # serialice: Vendor writes: + irq 0x14 = 0xd0 + irq 0x1c = 0xa8 + irq 0x1d = 0x01 + irq 0x22 = 0x3f + irq 0x1a = 0xa0 + # dumped from superiotool: + irq 0x1b = 0x1e + irq 0x27 = 0x08 + irq 0x2a = 0x00 + irq 0x2d = 0x21 + # parallel port + io 0x60 = 0x278 + irq 0x70 = 0x07 + drq 0x74 = 0x04 + end + device pnp 2e.2 off # COM1 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # COM2, IR + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # LED control + io 0x60 = 0x0a20 + # IOBASE[0h] = bit0 LED red / green + # IOBASE[0h] = bit1-4 LED PWM duty cycle + # IOBASE[1h] = bit6 SWCC + + io 0x62 = 0x0aa0 + # IOBASE [0h] = GPES + # IOBASE [1h] = GPEE + # IOBASE [4h:7h] = 32bit upcounter at 1Mhz + # IOBASE [8h:bh] = GPS + # IOBASE [ch:fh] = GPE + end + device pnp 2e.5 off # Mouse + irq 0x70 = 0xc + end + device pnp 2e.6 off # Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 0x01 + # serialice: Vendor writes: + drq 0xf0 = 0x40 + end + device pnp 2e.7 on # WDT ? + io 0x60 = 0x0a00 + end + device pnp 2e.8 off # HWM + io 0x60 = 0x0b00 + # IOBASE[0h:feh] HWM page + # IOBASE[ffh] bit0-bit3 page selector + + drq 0xf0 = 0x20 + drq 0xf1 = 0x01 + drq 0xf2 = 0x40 + drq 0xf3 = 0x01 + + drq 0xf4 = 0x66 + drq 0xf5 = 0x66 + drq 0xf6 = 0x66 + drq 0xf7 = 0x01 + end + device pnp 2e.f on # GPIO OD ? + drq 0xf1 = 0x97 + drq 0xf2 = 0x01 + drq 0xf5 = 0x0b + drq 0xfe = 0x80 + end + device pnp 2e.15 off # BUS ? + io 0x60 = 0x0000 + io 0x62 = 0x0000 + end + device pnp 2e.1c on # Suspend Control ? + io 0x60 = 0x0a60 + # writing to IOBASE[5h] + # 0x0: Power off + # 0x9: Power off and bricked until CMOS battery removed + end + device pnp 2e.1e off # GPIO ? + io 0x60 = 0x0000 + drq 0xf4 = 0x00 + # skip the following, as it + # looks like remapped registers + #drq 0xf5 = 0x06 + #drq 0xf6 = 0x60 + #drq 0xfe = 0x03 + end + end + end + end + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end + device pci 1f.2 on end # SATA Controller (AHCI) + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/hp/260_g1_dm/dsdt.asl b/src/mainboard/hp/260_g1_dm/dsdt.asl new file mode 100644 index 0000000000..2eb0805cf2 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/hp/260_g1_dm/gma-mainboard.ads b/src/mainboard/hp/260_g1_dm/gma-mainboard.ads new file mode 100644 index 0000000000..439aff80c1 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/gma-mainboard.ads @@ -0,0 +1,17 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP1, + HDMI1, + DP2, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/hp/260_g1_dm/gpio.c b/src/mainboard/hp/260_g1_dm/gpio.c new file mode 100644 index 0000000000..4f48be2737 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/gpio.c @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const struct pch_lp_gpio_map mainboard_lp_gpio_map[] = { + [0] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [1] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [2] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [3] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [4] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [5] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [6] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [7] = LP_GPIO_INPUT, + [8] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [9] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [10] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [11] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [12] = LP_GPIO_OUT_LOW, + [13] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [14] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [15] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [16] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [17] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [18] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [19] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [20] = LP_GPIO_NATIVE, + [21] = LP_GPIO_NATIVE, + [22] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [23] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [24] = LP_GPIO_OUT_LOW, + [25] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [26] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [27] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [28] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [29] = LP_GPIO_NATIVE, + [30] = LP_GPIO_NATIVE, + [31] = LP_GPIO_NATIVE, + [32] = LP_GPIO_NATIVE, + [33] = LP_GPIO_NATIVE, + [34] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .owner = GPIO_OWNER_GPIO }, + [35] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .owner = GPIO_OWNER_GPIO }, + [36] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [37] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [38] = LP_GPIO_NATIVE, + [39] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [40] = LP_GPIO_NATIVE, + [41] = LP_GPIO_NATIVE, + [42] = LP_GPIO_NATIVE, + [43] = LP_GPIO_NATIVE, + [44] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [45] = LP_GPIO_OUT_LOW, + [46] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [47] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [48] = LP_GPIO_PIRQ, + [49] = LP_GPIO_PIRQ, + [50] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [51] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [52] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [53] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [54] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [55] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO, + .pirq = GPIO_PIRQ_APIC_ROUTE + }, + [56] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [57] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [58] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [59] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [60] = LP_GPIO_NATIVE, + [61] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [62] = LP_GPIO_NATIVE, + [63] = LP_GPIO_NATIVE, + [64] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [65] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [66] = LP_GPIO_NATIVE, + [67] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [68] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [69] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [70] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [71] = LP_GPIO_NATIVE, + [72] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [73] = LP_GPIO_NATIVE, + [74] = LP_GPIO_NATIVE, + [75] = LP_GPIO_NATIVE, + [76] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [77] = LP_GPIO_INPUT, + [78] = LP_GPIO_INPUT, + [79] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [80] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [81] = LP_GPIO_NATIVE, + [82] = LP_GPIO_NATIVE, + [83] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [84] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [85] = LP_GPIO_INPUT, + [86] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT | GPIO_INVERT, .owner = GPIO_OWNER_GPIO }, + [87] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [88] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [89] = LP_GPIO_INPUT, + [90] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [91] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + [92] = LP_GPIO_INPUT, + [93] = LP_GPIO_INPUT, + [94] = { .conf0 = GPIO_MODE_GPIO | GPIO_DIR_INPUT, .owner = GPIO_OWNER_GPIO }, + LP_GPIO_END +}; diff --git a/src/mainboard/hp/260_g1_dm/hda_verb.c b/src/mainboard/hp/260_g1_dm/hda_verb.c new file mode 100644 index 0000000000..f3614d8910 --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0221, /* Codec Vendor / Device ID: Realtek */ + 0x103c8000, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x103c8000), + AZALIA_PIN_CFG(0, 0x12, 0x400c0000), + AZALIA_PIN_CFG(0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0, 0x17, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1a, 0x02a11030), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x40500001), + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, 0x0221102f), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/hp/260_g1_dm/romstage.c b/src/mainboard/hp/260_g1_dm/romstage.c new file mode 100644 index 0000000000..e5c559a2da --- /dev/null +++ b/src/mainboard/hp/260_g1_dm/romstage.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_config_rcba(void) +{ +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0080, 1, 1, USB_PORT_MINI_PCIE }, + { 0x0080, 1, 0, USB_PORT_MINI_PCIE }, + { 0x0040, 1, 3, USB_PORT_BACK_PANEL }, + { 0x0080, 1, 3, USB_PORT_DOCK }, + { 0x0080, 1, 2, USB_PORT_MINI_PCIE }, + { 0x0080, 1, 2, USB_PORT_MINI_PCIE }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, + { 0x0040, 1, 1, USB_PORT_BACK_PANEL }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 1 }, + { 1, 0 }, + { 1, 3 }, + { 1, 3 }, +};