RW: veyron_(gus|jaq|jerry|mighty): Increase SPI frequency in RW

Unfortunately, firmware for some Veyron boards was finalized before we
realized that we're clocking our SPI flash far lower than we need to.
Nothing we can do about that in RO now. We can, however, reinitialize
SPI in RW with a higher frequency to at least gain some speed back for
ramstage and payload load times on those boards.

BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Resigned a Jerry 6588.40.0 MP image with my own 4K keys, dd'ed the
last 2MB of an image with this patch onto it, confirmed 1.33s boot time.

Change-Id: I999aff125891e64123fdd7dc21f04640ac411583
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/263112
Reviewed-by: David Hendricks <dhendrix@chromium.org>

src/mainboard/google/veyron_gus/romstage.c

@@ -32,6 +32,7 @@
 #include <soc/pwm.h>
 #include <soc/grf.h>
 #include <soc/rk808.h>
+#include <soc/spi.h>
 #include <soc/tsadc.h>
 #include <stdlib.h>
 #include <symbols.h>
@@ -102,6 +103,9 @@ void main(void)
 	sdram_init(get_sdram_config());
 	timestamp_add_now(TS_AFTER_INITRAM);
 
+	/* Increase frequency in RW in case it was set up too low by old RO. */
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
 	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
 	mmu_config_range((uintptr_t)_dram/MiB,
 			 sdram_size_mb(), DCACHE_WRITEBACK);

src/mainboard/google/veyron_jaq/romstage.c

@@ -32,6 +32,7 @@
 #include <soc/pwm.h>
 #include <soc/grf.h>
 #include <soc/rk808.h>
+#include <soc/spi.h>
 #include <soc/tsadc.h>
 #include <stdlib.h>
 #include <symbols.h>
@@ -102,6 +103,9 @@ void main(void)
 	sdram_init(get_sdram_config());
 	timestamp_add_now(TS_AFTER_INITRAM);
 
+	/* Increase frequency in RW in case it was set up too low by old RO. */
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
 	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
 	mmu_config_range((uintptr_t)_dram/MiB,
 			 sdram_size_mb(), DCACHE_WRITEBACK);

src/mainboard/google/veyron_jerry/romstage.c

@@ -32,6 +32,7 @@
 #include <soc/pwm.h>
 #include <soc/grf.h>
 #include <soc/rk808.h>
+#include <soc/spi.h>
 #include <soc/tsadc.h>
 #include <stdlib.h>
 #include <symbols.h>
@@ -102,6 +103,9 @@ void main(void)
 	sdram_init(get_sdram_config());
 	timestamp_add_now(TS_AFTER_INITRAM);
 
+	/* Increase frequency in RW in case it was set up too low by old RO. */
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
 	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
 	mmu_config_range((uintptr_t)_dram/MiB,
 			 sdram_size_mb(), DCACHE_WRITEBACK);

src/mainboard/google/veyron_mighty/romstage.c

@@ -32,6 +32,7 @@
 #include <soc/pwm.h>
 #include <soc/grf.h>
 #include <soc/rk808.h>
+#include <soc/spi.h>
 #include <soc/tsadc.h>
 #include <stdlib.h>
 #include <symbols.h>
@@ -102,6 +103,9 @@ void main(void)
 	sdram_init(get_sdram_config());
 	timestamp_add_now(TS_AFTER_INITRAM);
 
+	/* Increase frequency in RW in case it was set up too low by old RO. */
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
 	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
 	mmu_config_range((uintptr_t)_dram/MiB,
 			 sdram_size_mb(), DCACHE_WRITEBACK);