diff --git a/src/mainboard/google/veyron_gus/romstage.c b/src/mainboard/google/veyron_gus/romstage.c
index e22a04e14b..293e1e2710 100644
--- a/src/mainboard/google/veyron_gus/romstage.c
+++ b/src/mainboard/google/veyron_gus/romstage.c
@@ -32,6 +32,7 @@
 #include <soc/pwm.h>
 #include <soc/grf.h>
 #include <soc/rk808.h>
+#include <soc/spi.h>
 #include <soc/tsadc.h>
 #include <stdlib.h>
 #include <symbols.h>
@@ -102,6 +103,9 @@ void main(void)
 	sdram_init(get_sdram_config());
 	timestamp_add_now(TS_AFTER_INITRAM);
 
+	/* Increase frequency in RW in case it was set up too low by old RO. */
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
 	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
 	mmu_config_range((uintptr_t)_dram/MiB,
 			 sdram_size_mb(), DCACHE_WRITEBACK);
diff --git a/src/mainboard/google/veyron_jaq/romstage.c b/src/mainboard/google/veyron_jaq/romstage.c
index e22a04e14b..293e1e2710 100644
--- a/src/mainboard/google/veyron_jaq/romstage.c
+++ b/src/mainboard/google/veyron_jaq/romstage.c
@@ -32,6 +32,7 @@
 #include <soc/pwm.h>
 #include <soc/grf.h>
 #include <soc/rk808.h>
+#include <soc/spi.h>
 #include <soc/tsadc.h>
 #include <stdlib.h>
 #include <symbols.h>
@@ -102,6 +103,9 @@ void main(void)
 	sdram_init(get_sdram_config());
 	timestamp_add_now(TS_AFTER_INITRAM);
 
+	/* Increase frequency in RW in case it was set up too low by old RO. */
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
 	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
 	mmu_config_range((uintptr_t)_dram/MiB,
 			 sdram_size_mb(), DCACHE_WRITEBACK);
diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c
index e22a04e14b..293e1e2710 100644
--- a/src/mainboard/google/veyron_jerry/romstage.c
+++ b/src/mainboard/google/veyron_jerry/romstage.c
@@ -32,6 +32,7 @@
 #include <soc/pwm.h>
 #include <soc/grf.h>
 #include <soc/rk808.h>
+#include <soc/spi.h>
 #include <soc/tsadc.h>
 #include <stdlib.h>
 #include <symbols.h>
@@ -102,6 +103,9 @@ void main(void)
 	sdram_init(get_sdram_config());
 	timestamp_add_now(TS_AFTER_INITRAM);
 
+	/* Increase frequency in RW in case it was set up too low by old RO. */
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
 	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
 	mmu_config_range((uintptr_t)_dram/MiB,
 			 sdram_size_mb(), DCACHE_WRITEBACK);
diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c
index e22a04e14b..293e1e2710 100644
--- a/src/mainboard/google/veyron_mighty/romstage.c
+++ b/src/mainboard/google/veyron_mighty/romstage.c
@@ -32,6 +32,7 @@
 #include <soc/pwm.h>
 #include <soc/grf.h>
 #include <soc/rk808.h>
+#include <soc/spi.h>
 #include <soc/tsadc.h>
 #include <stdlib.h>
 #include <symbols.h>
@@ -102,6 +103,9 @@ void main(void)
 	sdram_init(get_sdram_config());
 	timestamp_add_now(TS_AFTER_INITRAM);
 
+	/* Increase frequency in RW in case it was set up too low by old RO. */
+	rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
 	/* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
 	mmu_config_range((uintptr_t)_dram/MiB,
 			 sdram_size_mb(), DCACHE_WRITEBACK);