From d2e45eb766cbf99a82ba9233769bbe482e3cd59e Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Mon, 30 Mar 2015 13:14:33 -0700 Subject: [PATCH] RW: veyron_(gus|jaq|jerry|mighty): Increase SPI frequency in RW Unfortunately, firmware for some Veyron boards was finalized before we realized that we're clocking our SPI flash far lower than we need to. Nothing we can do about that in RO now. We can, however, reinitialize SPI in RW with a higher frequency to at least gain some speed back for ramstage and payload load times on those boards. BRANCH=veyron BUG=chrome-os-partner:38352 TEST=Resigned a Jerry 6588.40.0 MP image with my own 4K keys, dd'ed the last 2MB of an image with this patch onto it, confirmed 1.33s boot time. Change-Id: I999aff125891e64123fdd7dc21f04640ac411583 Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/263112 Reviewed-by: David Hendricks --- src/mainboard/google/veyron_gus/romstage.c | 4 ++++ src/mainboard/google/veyron_jaq/romstage.c | 4 ++++ src/mainboard/google/veyron_jerry/romstage.c | 4 ++++ src/mainboard/google/veyron_mighty/romstage.c | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/src/mainboard/google/veyron_gus/romstage.c b/src/mainboard/google/veyron_gus/romstage.c index e22a04e14b..293e1e2710 100644 --- a/src/mainboard/google/veyron_gus/romstage.c +++ b/src/mainboard/google/veyron_gus/romstage.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -102,6 +103,9 @@ void main(void) sdram_init(get_sdram_config()); timestamp_add_now(TS_AFTER_INITRAM); + /* Increase frequency in RW in case it was set up too low by old RO. */ + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); diff --git a/src/mainboard/google/veyron_jaq/romstage.c b/src/mainboard/google/veyron_jaq/romstage.c index e22a04e14b..293e1e2710 100644 --- a/src/mainboard/google/veyron_jaq/romstage.c +++ b/src/mainboard/google/veyron_jaq/romstage.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -102,6 +103,9 @@ void main(void) sdram_init(get_sdram_config()); timestamp_add_now(TS_AFTER_INITRAM); + /* Increase frequency in RW in case it was set up too low by old RO. */ + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index e22a04e14b..293e1e2710 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -102,6 +103,9 @@ void main(void) sdram_init(get_sdram_config()); timestamp_add_now(TS_AFTER_INITRAM); + /* Increase frequency in RW in case it was set up too low by old RO. */ + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK); diff --git a/src/mainboard/google/veyron_mighty/romstage.c b/src/mainboard/google/veyron_mighty/romstage.c index e22a04e14b..293e1e2710 100644 --- a/src/mainboard/google/veyron_mighty/romstage.c +++ b/src/mainboard/google/veyron_mighty/romstage.c @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -102,6 +103,9 @@ void main(void) sdram_init(get_sdram_config()); timestamp_add_now(TS_AFTER_INITRAM); + /* Increase frequency in RW in case it was set up too low by old RO. */ + rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz); + /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, sdram_size_mb(), DCACHE_WRITEBACK);