From d19dd192dbe31b49df71e9afb4abaf708b2d9f78 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 27 Feb 2025 09:20:34 -0800 Subject: [PATCH] mb/google/fatcat: Add PTL-U Fast VMode Voltage Regulator settings This commit introduces the missing Fast Voltage Mode settings for the Voltage Regulator (VR) applicable to the Intel Panther Lake (PTL)-U 15W System on Chip (SoC) on the Google Fatcat mainboard. The configurations have been populated in accordance with the specifications outlined in Intel's Panther Lake Power Map document (reference number 813278). These settings leverage the Fast Voltage Mode capabilities of the CPU cores (IA), Graphics (GT), and System Agent (SA). The voltage regulator settings are for PTL-U; therefore, when the coreboot image is used on a Panther Lake H SKU, some lower performance could be observed due to the I_TRIP value being lower than what the device could actually use. BUG=b:357011633 TEST=As no Panther Lake-U (PTL-U) SKUs were available, smoke tests have been performed on Panther Lake-H (PTL-H). We verified that the Firmware Support Package (FSP) successfully submitted requests to the pcode firmware and that once the operating system was running, S0iX entry and exit were operational. Change-Id: If98edb88d7488c0b863a8f1a9654d0273de567c6 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/86622 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- .../variants/baseboard/fatcat/devicetree.cb | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index b09f9e324b..f9c79adc8f 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -62,6 +62,23 @@ chip soc/intel/pantherlake # Enable Energy Reporting register "pch_pm_energy_report_enable" = "true" + # As per document 813278, the Intel PTL-U 15W SoC supports + # Fast V-Mode (FVM) on cores (IA), Graphics (GT), and System + # Agent (SA). The ICC Limit is represented in 1/4 A + # increments, i.e., a value of 400 = 100A. + # IA VR configuration + register "enable_fast_vmode[VR_DOMAIN_IA]" = "true" + register "cep_enable[VR_DOMAIN_IA]" = "true" + register "fast_vmode_i_trip[VR_DOMAIN_IA]" = "252" # 63A + # GT VR configuration + register "enable_fast_vmode[VR_DOMAIN_GT]" = "true" + register "cep_enable[VR_DOMAIN_GT]" = "true" + register "fast_vmode_i_trip[VR_DOMAIN_GT]" = "152" # 38A + # SA VR configuration + register "enable_fast_vmode[VR_DOMAIN_SA]" = "true" + register "cep_enable[VR_DOMAIN_SA]" = "true" + register "fast_vmode_i_trip[VR_DOMAIN_SA]" = "152" # 38A + # Enable CNVi BT register "cnvi_bt_core" = "true"