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samus: Disable self refresh and MRC cache on broadwell

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Workarounds for power and/or lpddr3 issues on broadwell SKU.

BUG=chrome-os-partner:29787,chrome-os-partner:29117
BRANCH=None
TEST=build and boot on samus

Change-Id: If99346212c10ad6026250e48bedd916611e2cb8c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/208154
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Duncan Laurie 2014-07-15 13:40:21 -07:00 • committed by chrome-internal-fetch
commit c3ee571143
1 changed files with 11 additions and 0 deletions
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11
src/mainboard/google/samus/romstage.c
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@ -22,6 +22,7 @@
#include <console/console.h>
#include <string.h>
#include <ec/google/chromeec/ec.h>
#include <broadwell/cpu.h>
#include <broadwell/gpio.h>
#include <broadwell/pei_data.h>
#include <broadwell/pei_wrapper.h>
@ -54,6 +55,16 @@ void mainboard_romstage_entry(struct romstage_params *rp)
mainboard_fill_spd_data(&pei_data);
rp->pei_data = &pei_data;
/*
* http://crosbug.com/p/29117
* Disable use of PEI saved data to work around memory issues.
*/
if (cpu_family_model() == BROADWELL_FAMILY_ULT) {
pei_data.disable_self_refresh = 1;
pei_data.disable_saved_data = 1;
}
/* Initliaze memory */
romstage_common(rp);
/*