From c3ee57114315320b542f53645ffb168ad654b756 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Tue, 15 Jul 2014 13:40:21 -0700 Subject: [PATCH] samus: Disable self refresh and MRC cache on broadwell Workarounds for power and/or lpddr3 issues on broadwell SKU. BUG=chrome-os-partner:29787,chrome-os-partner:29117 BRANCH=None TEST=build and boot on samus Change-Id: If99346212c10ad6026250e48bedd916611e2cb8c Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/208154 Reviewed-by: Aaron Durbin --- src/mainboard/google/samus/romstage.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index d6528592e4..2e1a71f5c5 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include #include @@ -54,6 +55,16 @@ void mainboard_romstage_entry(struct romstage_params *rp) mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; + /* + * http://crosbug.com/p/29117 + * Disable use of PEI saved data to work around memory issues. + */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) { + pei_data.disable_self_refresh = 1; + pei_data.disable_saved_data = 1; + } + + /* Initliaze memory */ romstage_common(rp); /*