diff --git a/src/mainboard/google/ocelot/variants/ojal/Makefile.mk b/src/mainboard/google/ocelot/variants/ojal/Makefile.mk index 4c33dad4db..3fdd4642c0 100644 --- a/src/mainboard/google/ocelot/variants/ojal/Makefile.mk +++ b/src/mainboard/google/ocelot/variants/ojal/Makefile.mk @@ -3,4 +3,8 @@ bootblock-y += gpio.c romstage-y += gpio.c romstage-y += memory.c +romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c +romstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/ocelot/variants/ojal/fw_config.c b/src/mainboard/google/ocelot/variants/ojal/fw_config.c new file mode 100644 index 0000000000..a658e76542 --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/fw_config.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +/* t: base table; o: override table */ +#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o)) +/* t: table */ +#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t)) + +static const struct pad_config pre_mem_gen4_ssd_pwr_pads[] = { + /* GPP_H18: GEN4_SSD_PWREN */ + PAD_CFG_GPO(GPP_H18, 0, PLTRST), +}; + +static const struct pad_config gen4_ssd_pads[] = { + /* GPP_H18: GEN4_SSD_PWREN */ + PAD_CFG_GPO(GPP_H18, 1, PLTRST), + /* GPP_A08: M2_GEN4_SSD_RESET_N */ + PAD_CFG_GPO(GPP_A08, 1, PLTRST), +}; + +static const struct pad_config ufs_enable_pads[] = { + /* GPP_D21: GPP_D21_UFS_REFCLK */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +}; + +static const struct pad_config cnvi_enable_pads[] = { + /* GPP_B09: BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_B09, 1, DEEP), + /* GPP_C10: WIFI_RF_KILL_N */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RESET_R_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CRF_CLKREQ_R */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), +}; + +static const struct pad_config cnvi_disable_pads[] = { + /* GPP_B09: BT_RF_KILL_N */ + PAD_NC(GPP_B09, NONE), + /* GPP_C10: WIFI_RF_KILL_N */ + PAD_NC(GPP_C10, NONE), + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + PAD_NC(GPP_F00, NONE), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + PAD_NC(GPP_F01, NONE), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + PAD_NC(GPP_F02, NONE), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + PAD_NC(GPP_F03, NONE), + /* GPP_F04: CNV_RF_RESET_R_N */ + PAD_NC(GPP_F04, NONE), + /* GPP_F05: CRF_CLKREQ_R */ + PAD_NC(GPP_F05, NONE), +}; + +void fw_config_configure_pre_mem_gpio(void) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); + return; + } + + if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); + } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { + GPIO_CONFIGURE_PADS(pre_mem_gen4_ssd_pwr_pads); + } +} + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + //const struct soc_intel_pantherlake_config *config = config_of_soc(); + + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); + return; + } + + if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME_GEN4))) { + GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads); + } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UFS))) { + GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads); + } else if (fw_config_probe(FW_CONFIG(STORAGE, STORAGE_UNKNOWN))) { + GPIO_PADBASED_OVERRIDE(padbased_table, gen4_ssd_pads); + GPIO_PADBASED_OVERRIDE(padbased_table, ufs_enable_pads); + } + + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) || + fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) { + GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_enable_pads); + } else if (fw_config_probe(FW_CONFIG(WIFI, WIFI_NONE))) { + GPIO_PADBASED_OVERRIDE(padbased_table, cnvi_disable_pads); + } +} diff --git a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb index 47cdd94f4b..4394314a24 100644 --- a/src/mainboard/google/ocelot/variants/ojal/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ojal/overridetree.cb @@ -1,5 +1,273 @@ +fw_config + field AUDIO 0 1 + option AUDIO_NONE 0 + option AUDIO_CS42L43_SNDW 1 + option AUDIO_ALC256_HDA 2 + end + field WIFI 2 3 + option WIFI_NONE 0 + option WIFI_CNVI_6 1 + option WIFI_CNVI_7 2 + end + field TOUCHPAD 4 5 + option TOUCHPAD_NONE 0 + option TOUCHPAD_LPSS_I2C 1 + end + field STORAGE 6 7 + option STORAGE_UNKNOWN 0 + option STORAGE_NVME_GEN4 1 + option STORAGE_UFS 2 + end + field FP 8 + option FP_ABSENT 0 + option FP_PRESENT 1 + end + field DISPLAY 9 + option DISPLAY_ABSENT 0 + option DISPLAY_PRESENT 1 + end + field ISH 10 + option ISH_DISABLE 0 + option ISH_ENABLE 1 + end + field KB 11 + option KB_ABSENT 0 + option KB_PRESENT 1 + end +end + chip soc/intel/pantherlake - device domain 0 on - end + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP0 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type C port - various configurations - TCP1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # USB3.2 Gen2x1 Type-A Port + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # 2x5 USB2 HDR + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB 3.2 Gen2 x1 Type-A Con - # 2 + + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "tcss_cap_policy[0]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[1]" = "TCSS_TYPE_C_PORT_FULL_FUN" + + # Enable EDP in PortA & HDMI in Port B + register "ddi_port_A_config" = "1" + register "ddi_port_B_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI0A] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Touchpad | + #| I2C1 | TPM(cr50) | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + /* Render OEM footer logo 100px above from the edge */ + .logo_bottom_margin = 100, + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .early_init = 1, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device ref igpu on + probe DISPLAY DISPLAY_PRESENT + chip drivers/gfx/generic + register "device_count" = "5" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) for port C1 + register "device[3].name" = ""DD03"" + register "device[3].use_pld" = "true" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device generic 0 on end + end + end + + device ref iaa off end + + device ref tbt_pcie_rp0 on end + device ref tbt_pcie_rp1 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + end + end + end + + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port1 as dfp[1].typec_port + device generic 0 on end + end + end + + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 2"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 4"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(6, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 5"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(7, 1)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 2"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on end + end + end + end + end + + device ref ufs on + probe STORAGE STORAGE_UFS + probe STORAGE STORAGE_UNKNOWN + end + + device ref pcie_rp1 on + probe STORAGE STORAGE_NVME_GEN4 + probe STORAGE STORAGE_UNKNOWN + register "pcie_rp[PCIE_RP(1)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end # Gen4 M.2 SSD + + device ref cnvi_wifi on + probe WIFI WIFI_CNVI_6 + probe WIFI WIFI_CNVI_7 + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + use cnvi_bluetooth as bluetooth_companion + device generic 0 on end + end + end # CNVi + + device ref cnvi_bluetooth on + probe WIFI WIFI_CNVI_6 + probe WIFI WIFI_CNVI_7 + end + + device ref i2c0 on end + + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B17_IRQ)" + device i2c 50 on end + end + end + + device ref smbus on end + end end diff --git a/src/mainboard/google/ocelot/variants/ojal/variant.c b/src/mainboard/google/ocelot/variants/ojal/variant.c new file mode 100644 index 0000000000..4aa9adeabe --- /dev/null +++ b/src/mainboard/google/ocelot/variants/ojal/variant.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI)); +} + +void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config) +{ + /* CNVi */ + if (fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_6)) || + fw_config_probe(FW_CONFIG(WIFI, WIFI_CNVI_7))) { + config->cnvi_wifi_core = true; + config->cnvi_bt_core = true; + } +} + +void variant_update_soc_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; + + /* HDA Audio */ + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) { + printk(BIOS_INFO, "Overriding HDA SDI lanes.\n"); + m_cfg->PchHdaSdiEnable[0] = true; + m_cfg->PchHdaSdiEnable[1] = false; + } +}