From bd858faee8ef6d71a8742808167662ccca259933 Mon Sep 17 00:00:00 2001 From: Maximilian Brune Date: Tue, 18 Nov 2025 23:20:35 +0100 Subject: [PATCH] mb/amd/crater: Add XGBE support If XGBE is used on the platform, it can be configured to match different use cases. Change-Id: Ia6f7c2b836050e52bfb1d9ff64745d83715c874b Signed-off-by: Maximilian Brune Reviewed-on: https://review.coreboot.org/c/coreboot/+/90104 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/amd/crater/Kconfig | 52 ++++++ src/mainboard/amd/crater/Makefile.mk | 2 + src/mainboard/amd/crater/ec.c | 29 ++++ src/mainboard/amd/crater/ec.h | 1 + .../amd/crater/port_descriptors_renoir.c | 151 +++++++++++++++++- 5 files changed, 233 insertions(+), 2 deletions(-) diff --git a/src/mainboard/amd/crater/Kconfig b/src/mainboard/amd/crater/Kconfig index 1560201ea3..cc15d467ab 100644 --- a/src/mainboard/amd/crater/Kconfig +++ b/src/mainboard/amd/crater/Kconfig @@ -112,6 +112,58 @@ config PCIE_DT_SLOT endchoice +choice + prompt "SGMII lanes interface" + depends on XGBE_WWAN_WLAN + default GBE_PATH_SELECT_AIC2 + help + Option to select either AIC2 card (Marvell Phy), AIC3 card (Broadcom Phy) or + Backplane mode for SGMII + +config GBE_PATH_SELECT_AIC2 + bool "AIC2 PHY" + help + Select to use AIC2 Marvell Phy card + +config GBE_PATH_SELECT_AIC3 + bool "AIC3 PHY" + help + Select to use AIC3 Boradcom Phy card + +config XGBE_PATH_SELECT_BACKPLANE + bool "BackPlane" + help + Select to use BackPlane Mode + +endchoice # "SGMII lanes interface" + +choice + prompt "XGBE port speed" + depends on XGBE_WWAN_WLAN && !XGBE_PATH_SELECT_BACKPLANE + default XGBE_10_100_1000MB_SPEED + +config XGBE_10_100_1000MB_SPEED + bool "10/100/1000MB" + help + Set XGBE port speed to support 10/100/1000MB. + +config XGBE_10MB_SPEED + bool "10MB Port Speed" + help + Set XGBE port speed to support 10MBps. + +config XGBE_100MB_SPEED + bool "100 MBps port speed" + help + Set XGBE port speed to support 1000MBps. + +config XGBE_1G_SPEED + bool "1G Port Speed" + help + Set XGBE port speed to support 1GBps. + +endchoice # "XGBE port speed" + if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE default 3 # Quad IO (1-1-4) diff --git a/src/mainboard/amd/crater/Makefile.mk b/src/mainboard/amd/crater/Makefile.mk index 3207c59c5c..8380fc6fef 100644 --- a/src/mainboard/amd/crater/Makefile.mk +++ b/src/mainboard/amd/crater/Makefile.mk @@ -4,10 +4,12 @@ bootblock-y += bootblock.c bootblock-y += early_gpio.c bootblock-y += ec.c +romstage-y += ec.c romstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c ramstage-y += chromeos.c ramstage-y += gpio.c +ramstage-y += ec.c ramstage-$(CONFIG_BOARD_AMD_CRATER_RENOIR) += port_descriptors_renoir.c ifneq ($(wildcard $(MAINBOARD_BLOBS_DIR)/APCB_RN_D4_Updatable.bin),) diff --git a/src/mainboard/amd/crater/ec.c b/src/mainboard/amd/crater/ec.c index e9a947523f..533e32de25 100644 --- a/src/mainboard/amd/crater/ec.c +++ b/src/mainboard/amd/crater/ec.c @@ -106,6 +106,8 @@ #define ECRAM_BOARDID_OFFSET 0x93 #define CRATER_REVB 0x42 +#define ECRAM_MACID_OFFSET 0x54 +#define MACID_LEN 12 static void configure_ec_gpio(void) { @@ -211,3 +213,30 @@ void crater_ec_init(void) crater_boardrevision(); configure_ec_gpio(); } + +void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_mac) +{ + uint64_t port0_mac = 0; + uint64_t port1_mac = 0; + uint8_t value = 0; + uint8_t index = 0; + uint8_t offset = ECRAM_MACID_OFFSET; + + ec_set_ports(CRATER_EC_CMD, CRATER_EC_DATA); + for (index = 0; index < MACID_LEN; index++) { + value = ec_read(offset + index); + printk(BIOS_SPEW, "READ MACID REG 0x%2x Value 0x%02x\n", offset - index, value); + + if (index < 6) { + port0_mac = (port0_mac << 8) | value; + } else { + port1_mac = (port1_mac << 8) | value; + } + } + + printk(BIOS_SPEW, "MAC Address XGBE port0: 0x%02llx\n", port0_mac); + printk(BIOS_SPEW, "MAC Address XGBE port1: 0x%02llx\n", port1_mac); + + *xgbe_port0_mac = port0_mac; + *xgbe_port1_mac = port1_mac; +} diff --git a/src/mainboard/amd/crater/ec.h b/src/mainboard/amd/crater/ec.h index 9dd5cbca1b..f9e90a5244 100644 --- a/src/mainboard/amd/crater/ec.h +++ b/src/mainboard/amd/crater/ec.h @@ -5,5 +5,6 @@ void crater_ec_init(void); void crater_boardrevision(void); +void crater_ec_get_mac_addresses(uint64_t *xgbe_port0_mac, uint64_t *xgbe_port1_mac); #endif /* CRATER_EC_H */ diff --git a/src/mainboard/amd/crater/port_descriptors_renoir.c b/src/mainboard/amd/crater/port_descriptors_renoir.c index cfc6e2f35c..f24eb874a0 100644 --- a/src/mainboard/amd/crater/port_descriptors_renoir.c +++ b/src/mainboard/amd/crater/port_descriptors_renoir.c @@ -10,8 +10,8 @@ #include #include -#define ECRAM_MACID_OFFSET 0x54 -#define MACID_LEN 12 +#include +#include "ec.h" #define ECRAM_BOARDID_OFFSET 0x93 @@ -200,3 +200,150 @@ void mainboard_get_dxio_ddi_descriptors( *ddi_descs = crater_ddi_descriptors; *ddi_num = ARRAY_SIZE(crater_ddi_descriptors); } + +#if CONFIG(XGBE_PATH_SELECT_BACKPLANE) + +#define xgbe_port0_table_descriptor { \ + .xgbe_port_config = XGBE_PORT_DISABLE, \ + .xgbe_port_connected_type = XGBE_BACKPLANE_CONNECTION, \ + .xgbe_port_platform_config = BACKPLANE_AUTONEG_OFF, \ + .xgbe_port_supported_speed = XGBE_PORT_SPEED_1G, \ + .xgba_port_pad_mdio = 0x0, \ + .xgba_port_pad_i2c = 0x1, \ + .xgbe_port_sfp_tx_fault_gpio = 0xE, \ + .xgbe_port_sfp_rx_los_gpio = 0xD, \ + .xgbe_port_sfp_mod_abs_gpio = 0xC, \ + .xgbe_port_sfp_twi_bus = 0x1, \ + .xgbe_port_mdio_reset_type = 0x0, \ + .xgbe_port_reset_gpio_num = 0x0, \ + .xgbe_port_mdio_reset_i2c_address = 0x0, \ + .xgbe_port_sfp_i2c_address = 0x1, \ + .xgbe_port_sfp_gpio_mask = 0x2, \ + .xgbe_port_sfp_rs_gpio = 0x0, \ + .xgba_port_redriver_model = 0x0, \ + .xgba_port_redriver_interface = 0x1, \ + .xgba_port_redriver_address = 0x0, \ + .xgba_port_redriver_lane = 0x0, \ + .xgbe_port_sfp_twi_address = 0x1C, \ + .xgba_port_pad_gpio = 0x0, \ + .reserve1 = 0x0, \ + .xgbe_port_mdio_id = 0x0, \ +} +#define xgbe_port1_table_descriptor { \ + .xgbe_port_config = XGBE_PORT_DISABLE, \ + .xgbe_port_connected_type = XGBE_BACKPLANE_CONNECTION, \ + .xgbe_port_platform_config = BACKPLANE_AUTONEG_OFF, \ + .xgbe_port_supported_speed = XGBE_PORT_SPEED_1G, \ + .xgba_port_pad_mdio = 0x0, \ + .xgbe_port_mdio_id = 0x0, \ + .xgba_port_pad_i2c = 0x1, \ + .xgbe_port_sfp_tx_fault_gpio = 0xA, \ + .xgbe_port_sfp_rx_los_gpio = 0x9, \ + .xgbe_port_sfp_mod_abs_gpio = 0x8, \ + .xgbe_port_sfp_twi_bus = 0x2, \ + .xgbe_port_mdio_reset_type = 0x0, \ + .xgbe_port_reset_gpio_num = 0x0, \ + .xgbe_port_mdio_reset_i2c_address = 0x0, \ + .xgbe_port_sfp_i2c_address = 0x1, \ + .xgbe_port_sfp_gpio_mask = 0x2, \ + .xgbe_port_sfp_rs_gpio = 0x0, \ + .xgba_port_redriver_model = 0x0, \ + .xgba_port_redriver_interface = 0x1, \ + .xgba_port_redriver_address = 0x0, \ + .xgba_port_redriver_lane = 0x0, \ + .xgbe_port_sfp_twi_address = 0x1C, \ + .xgba_port_pad_gpio = 0x0, \ + .reserve1 = 0x0, \ +} + +#else + +#define xgbe_port0_table_descriptor { \ + .xgbe_port_config = XGBE_PORT_DISABLE, \ + .xgbe_port_connected_type = XGBE_CONNECTION_MDIO_PHY, \ + .xgbe_port_platform_config = XGBE_SOLDERED_DOWN_1000BASE_T, \ + .xgbe_port_supported_speed = CONFIG(XGBE_1G_SPEED) ? XGBE_PORT_SPEED_1G : \ + CONFIG(XGBE_100MB_SPEED) ? XGBE_PORT_SPEED_100M : \ + CONFIG(XGBE_10MB_SPEED) ? XGBE_PORT_SPEED_10M : XGBE_PORT_SPEED_10_100_1000M, \ + .xgba_port_pad_mdio = 0x1, \ + .xgba_port_pad_i2c = 0x0, \ + .xgbe_port_sfp_tx_fault_gpio = 0xB, \ + .xgbe_port_sfp_rx_los_gpio = 0xD, \ + .xgbe_port_sfp_mod_abs_gpio = 0xC, \ + .xgbe_port_sfp_twi_bus = 0x0, \ + .xgbe_port_mdio_reset_type = 0x0, \ + .xgbe_port_reset_gpio_num = 0x0, \ + .xgbe_port_mdio_reset_i2c_address = 0x0, \ + .xgbe_port_sfp_i2c_address = 0x1, \ + .xgbe_port_sfp_gpio_mask = 0x2, \ + .xgbe_port_sfp_rs_gpio = 0x0, \ + .xgba_port_redriver_model = 0x0, \ + .xgba_port_redriver_interface = 0x1, \ + .xgba_port_redriver_address = 0x0, \ + .xgba_port_redriver_lane = 0x0, \ + .xgbe_port_sfp_twi_address = 0x1C, \ + .xgba_port_pad_gpio = 0x0, \ + .reserve1 = 0x0, \ + .xgbe_port_mdio_id = 0x0, \ +} +#define xgbe_port1_table_descriptor { \ + .xgbe_port_config = XGBE_PORT_DISABLE, \ + .xgbe_port_connected_type = XGBE_CONNECTION_MDIO_PHY, \ + .xgbe_port_platform_config = XGBE_SOLDERED_DOWN_1000BASE_T, \ + .xgbe_port_supported_speed = CONFIG(XGBE_1G_SPEED) ? XGBE_PORT_SPEED_1G : \ + CONFIG(XGBE_100MB_SPEED) ? XGBE_PORT_SPEED_100M : \ + CONFIG(XGBE_10MB_SPEED) ? XGBE_PORT_SPEED_10M : XGBE_PORT_SPEED_10_100_1000M, \ + .xgba_port_pad_mdio = CONFIG(GBE_PATH_SELECT_AIC3) ? 0x2 : CONFIG(GBE_PATH_SELECT_AIC3) ? 0x01 : 0x0, \ + .xgbe_port_mdio_id = CONFIG(GBE_PATH_SELECT_AIC3) ? 0x0 : CONFIG(GBE_PATH_SELECT_AIC3) ? 0x01 : 0x0, \ + .xgba_port_pad_i2c = 0x0, \ + .xgbe_port_sfp_tx_fault_gpio = 0xA, \ + .xgbe_port_sfp_rx_los_gpio = 0x9, \ + .xgbe_port_sfp_mod_abs_gpio = 0x8, \ + .xgbe_port_sfp_twi_bus = 0x1, \ + .xgbe_port_mdio_reset_type = 0x0, \ + .xgbe_port_reset_gpio_num = 0x0, \ + .xgbe_port_mdio_reset_i2c_address = 0x0, \ + .xgbe_port_sfp_i2c_address = 0x1, \ + .xgbe_port_sfp_gpio_mask = 0x2, \ + .xgbe_port_sfp_rs_gpio = 0x0, \ + .xgba_port_redriver_model = 0x0, \ + .xgba_port_redriver_interface = 0x1, \ + .xgba_port_redriver_address = 0x0, \ + .xgba_port_redriver_lane = 0x0, \ + .xgbe_port_sfp_twi_address = 0x1C, \ + .xgba_port_pad_gpio = 0x0, \ + .reserve1 = 0x0, \ +} + +#endif + +static void xgbe_init(FSP_M_CONFIG *mcfg) +{ + static struct xgbe_port_table xgbe_port[2] = { + xgbe_port0_table_descriptor, + xgbe_port1_table_descriptor + }; + + /* MAC can be updated here to pass the same to FSP */ + crater_ec_get_mac_addresses(&mcfg->xgbe_port0_mac, &mcfg->xgbe_port1_mac); + printk(BIOS_SPEW, "MAC Address XGBE port0: 0x%02llx\n", mcfg->xgbe_port0_mac); + printk(BIOS_SPEW, "MAC Address XGBE port1: 0x%02llx\n", mcfg->xgbe_port1_mac); + + mcfg->xgbe_port0_config_en = is_dev_enabled(DEV_PTR(xgbe_0)); + mcfg->xgbe_port1_config_en = is_dev_enabled(DEV_PTR(xgbe_1)); + + if (mcfg->xgbe_port0_config_en) { + xgbe_port[0].xgbe_port_config = XGBE_PORT_ENABLE; + mcfg->xgbe_port0_table = (uint32_t)(uintptr_t)&xgbe_port[0]; + } + + if (mcfg->xgbe_port1_config_en) { + xgbe_port[1].xgbe_port_config = XGBE_PORT_ENABLE; + mcfg->xgbe_port1_table = (uint32_t)(uintptr_t)&xgbe_port[1]; + } +} + +void mb_pre_fspm(FSP_M_CONFIG *mcfg) +{ + xgbe_init(mcfg); +}