From bb3a484e36ef594c2870ce355d560089af2fee06 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Thu, 12 Jun 2025 10:15:11 -0700 Subject: [PATCH] soc/intel/*/acpi: Move the BASE ACPI method to northbridge The BASE method, previously located within USB Type-C Subsystem (TCSS) ASL (ACPI Source Language) scope across multiple Intel System on Chip (SoC) files, has been moved to the northbridge module. This refactoring allows the BASE method to be utilized beyond the USB Type-C Subsystem use-case. The BASE method calculates the PCIe device base address using function and device numbers. Note: the BASE method is now under the \SB.PCI0 scope. It used to be under the \_SB scope while only consumed by devices under the \SB.PCI0 scope. TEST=On a Fatcat board, we verified that the BASE method returns 0xE00A3000 for the "./acpidbg -b 'evaluate \_SB.PCI0.BASE 0x140003'" command. We performed a non-regression test as well on the TCSS DMA TDM0 device, which uses the BASE method, by verifying that "./acpidbg -b 'evaluate \_SB.PCI0.TDM0.DMAD'" and "./acpidbg -b 'evaluate \_SB.PCI0.TDM0.VDID'" return 0x22 and 0xE4338086, respectively. Change-Id: I431206e9f38a2a5695c90d4ae6d823fb231814aa Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/88084 Tested-by: build bot (Jenkins) Reviewed-by: Wonkyu Kim Reviewed-by: Sean Rhodes Reviewed-by: Subrata Banik --- src/soc/intel/alderlake/acpi/tcss.asl | 10 ---------- src/soc/intel/apollolake/acpi/northbridge.asl | 10 ++++++++++ src/soc/intel/common/block/acpi/acpi/northbridge.asl | 10 ++++++++++ src/soc/intel/meteorlake/acpi/tcss.asl | 10 ---------- src/soc/intel/pantherlake/acpi/tcss.asl | 10 ---------- src/soc/intel/tigerlake/acpi/tcss.asl | 10 ---------- 6 files changed, 20 insertions(+), 40 deletions(-) diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index b8b9fa4175..f184016f59 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -42,16 +42,6 @@ Scope (\_SB) { - /* Device base address */ - Method (BASE, 1) - { - Local0 = Arg0 & 0x7 /* Function number */ - Local1 = (Arg0 >> 16) & 0x1F /* Device number */ - Local2 = (Local0 << 12) + (Local1 << 15) - Local3 = \_SB.PCI0.GPCB() + Local2 - Return (Local3) - } - /* * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be * found in Device 31, Function 2, Offset 40h. diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index fcbd1d0494..3e3f177b97 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -131,5 +131,15 @@ Method (GPCB, 0, Serialized) Return (Local0) } +/* Device base address */ +Method (BASE, 1) +{ + Local0 = Arg0 & 0x7 /* Function number */ + Local1 = (Arg0 >> 16) & 0x1F /* Device number */ + Local2 = (Local0 << 12) + (Local1 << 15) + Local3 = \_SB.PCI0.GPCB() + Local2 + Return (Local3) +} + /* GFX 00:02.0 */ #include diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index dd176e600a..3b2fb85933 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -277,6 +277,16 @@ Method (GDMB, 0, Serialized) Return (Local0) } +/* Device base address */ +Method (BASE, 1) +{ + Local0 = Arg0 & 0x7 /* Function number */ + Local1 = (Arg0 >> 16) & 0x1F /* Device number */ + Local2 = (Local0 << 12) + (Local1 << 15) + Local3 = \_SB.PCI0.GPCB() + Local2 + Return (Local3) +} + /* PCI Device Resource Consumption */ Device (PDRC) { diff --git a/src/soc/intel/meteorlake/acpi/tcss.asl b/src/soc/intel/meteorlake/acpi/tcss.asl index b765f0c738..27785ea5bb 100644 --- a/src/soc/intel/meteorlake/acpi/tcss.asl +++ b/src/soc/intel/meteorlake/acpi/tcss.asl @@ -42,16 +42,6 @@ Scope (\_SB) { - /* Device base address */ - Method (BASE, 1) - { - Local0 = Arg0 & 0x7 /* Function number */ - Local1 = (Arg0 >> 16) & 0x1F /* Device number */ - Local2 = (Local0 << 12) + (Local1 << 15) - Local3 = \_SB.PCI0.GPCB() + Local2 - Return (Local3) - } - /* * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be * found in Device 31, Function 2, Offset 40h. diff --git a/src/soc/intel/pantherlake/acpi/tcss.asl b/src/soc/intel/pantherlake/acpi/tcss.asl index a89d26fb25..88c3ea7ba5 100644 --- a/src/soc/intel/pantherlake/acpi/tcss.asl +++ b/src/soc/intel/pantherlake/acpi/tcss.asl @@ -42,16 +42,6 @@ Scope (\_SB) { - /* Device base address */ - Method (BASE, 1) - { - Local0 = Arg0 & 0x7 /* Function number */ - Local1 = (Arg0 >> 16) & 0x1F /* Device number */ - Local2 = (Local0 << 12) + (Local1 << 15) - Local3 = \_SB.PCI0.GPCB() + Local2 - Return (Local3) - } - /* * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be * found in Device 31, Function 2, Offset 40h. diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index d01cf250aa..56a0e55fbd 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -42,16 +42,6 @@ Scope (\_SB) { - /* Device base address */ - Method (BASE, 1) - { - Local0 = Arg0 & 0x7 /* Function number */ - Local1 = (Arg0 >> 16) & 0x1F /* Device number */ - Local2 = (Local0 << 12) + (Local1 << 15) - Local3 = \_SB.PCI0.GPCB() + Local2 - Return (Local3) - } - /* * Define PCH ACPIBASE IO as an ACPI operating region. The base address can be * found in Device 31, Function 2, Offset 40h.