From ba0206ab76fe0b6834a14dc57f400d139094623c Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 1 May 2014 11:25:14 -0700 Subject: [PATCH] broadwell: Clean up the bootblock code - Use the PCI device ID macros for device addressing - Use the IO map defines from broadwell/iomap.h - Clean up some macro defines that were renamed - Clean up comments BUG=chrome-os-partner:28234 TEST=None Change-Id: I2c1e0bc397f6a58fb51406835a9aa37f1c049b0a Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/198925 Reviewed-by: Aaron Durbin --- .../intel/broadwell/bootblock/Makefile.inc | 1 + src/soc/intel/broadwell/bootblock/cpu.c | 14 ++------ src/soc/intel/broadwell/bootblock/pch.c | 36 ++++++++----------- .../intel/broadwell/bootblock/systemagent.c | 9 +++-- 4 files changed, 23 insertions(+), 37 deletions(-) create mode 100644 src/soc/intel/broadwell/bootblock/Makefile.inc diff --git a/src/soc/intel/broadwell/bootblock/Makefile.inc b/src/soc/intel/broadwell/bootblock/Makefile.inc new file mode 100644 index 0000000000..2ca5a4569f --- /dev/null +++ b/src/soc/intel/broadwell/bootblock/Makefile.inc @@ -0,0 +1 @@ +chipset_bootblock_inc += $(src)/soc/intel/broadwell/bootblock/timestamp.inc diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 05441352a2..11f1833fd0 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -23,23 +23,15 @@ #include #include #include - #include -#include "haswell.h" - -#if CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT -/* Needed for RCBA access to set Soft Reset Data register */ -#include -#else -#error "CPU must be paired with Intel LynxPoint southbridge" -#endif +#include +#include static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) { /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; @@ -55,7 +47,7 @@ static void enable_rom_caching(void) disable_cache(); /* Why only top 4MiB ? */ - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); + set_var_mtrr(1, CACHE_ROM_BASE, CONFIG_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); enable_cache(); /* Enable Variable MTRRs */ diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index b1f3d1e06a..9e76f7976f 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -19,17 +19,21 @@ #include #include -#include "pch.h" +#include +#include +#include +#include +#include static void store_initial_timestamp(void) { - /* On Cougar Point we have two 32bit scratchpad registers available: + /* Two 32bit scratchpad registers available: * D0:F0 0xdc (SKPAD) * D31:F2 0xd0 (SATA SP) */ tsc_t tsc = rdtsc(); - pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); + pci_write_config32(SA_DEV_ROOT, 0xdc, tsc.lo); + pci_write_config32(PCH_DEV_SATA, 0xd0, tsc.hi); } /* @@ -37,23 +41,16 @@ static void store_initial_timestamp(void) */ static void enable_spi_prefetch(void) { - u8 reg8; - device_t dev; - - dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); + u8 reg8 = pci_read_config8(PCH_DEV_LPC, 0xdc); reg8 &= ~(3 << 2); reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(PCH_DEV_LPC, 0xdc, reg8); } static void map_rcba(void) { - device_t dev = PCI_DEV(0, 0x1f, 0); - - pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1); + pci_write_config32(PCH_DEV_LPC, RCBA, RCBA_BASE_ADDRESS | 1); } static void enable_port80_on_lpc(void) @@ -71,18 +68,18 @@ static void set_spi_speed(void) u8 ssfc; /* Observe SPI Descriptor Component Section 0 */ - SPIBAR32(FDOC) = 0x1000; + SPIBAR32(SPIBAR_FDOC) = 0x1000; /* Extract the Write/Erase SPI Frequency from descriptor */ - fdod = SPIBAR32(FDOD); + fdod = SPIBAR32(SPIBAR_FDOD); fdod >>= 24; fdod &= 7; /* Set Software Sequence frequency to match */ - ssfc = SPIBAR8(SSFC + 2); + ssfc = SPIBAR8(SPIBAR_SSFC + 2); ssfc &= ~7; ssfc |= fdod; - SPIBAR8(SSFC + 2) = ssfc; + SPIBAR8(SPIBAR_SSFC + 2) = ssfc; } static void bootblock_southbridge_init(void) @@ -94,7 +91,4 @@ static void bootblock_southbridge_init(void) enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); - - /* Enable upper 128bytes of CMOS */ - RCBA32(RC) = (1 << 2); } diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index fcb0cd058c..b2dd27b1a1 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -18,9 +18,8 @@ */ #include - -/* Just re-define this instead of including haswell.h. It blows up romcc. */ -#define PCIEXBAR 0x60 +#include +#include static void bootblock_northbridge_init(void) { @@ -39,7 +38,7 @@ static void bootblock_northbridge_init(void) * 4GiB. */ reg = 0; - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); + pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg); }