From b117179256a192c2229ae36683ac5256e24e6a92 Mon Sep 17 00:00:00 2001 From: Mario Scheithauer Date: Tue, 27 Jan 2026 10:21:22 +0100 Subject: [PATCH] mb/siemens/{mc_ehl2,mc_ehl5}: Fine-tune Gen1 TX Output De-Emphasis for PCIe RP #7 On these two mainboards, a Gen1 device is connected on PCIe RP #7. Measurements have shown that a value of -0.137 dB yields an optimal eye TX mask test. BUG=none TEST=Eye TX mask test for PCIe RP #7 passed using an oscilloscope Change-Id: I2d95e50473e39c325531c6071773a6a3cbb3a1a0 Signed-off-by: Mario Scheithauer Reviewed-on: https://review.coreboot.org/c/coreboot/+/90945 Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) --- src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 5 +++++ src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 4a7a997446..c1ebf7b5be 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -62,6 +62,11 @@ chip soc/intel/elkhartlake register "PcieRpLtrDisable[1]" = "true" register "PcieRpLtrDisable[6]" = "true" + # Adjust TX Output De-Emphasis for PCIe RP7 to -0.137 dB + register "pcie_mp_cfg[6]" = "{ + .tx_gen1_de_emph = 0x3f, + }" + # Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1" diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb index bcd76cb991..5fca41cd4b 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl5/devicetree.cb @@ -62,6 +62,11 @@ chip soc/intel/elkhartlake register "PcieRpLtrDisable[1]" = "true" register "PcieRpLtrDisable[6]" = "true" + # Adjust TX Output De-Emphasis for PCIe RP7 to -0.137 dB + register "pcie_mp_cfg[6]" = "{ + .tx_gen1_de_emph = 0x3f, + }" + # Storage (SDCARD/EMMC) related UPDs register "ScsEmmcHs400Enabled" = "0" register "ScsEmmcDdr50Enabled" = "1"