From b03b42285e1e610dd9af822e5111c5d0b468fd5a Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 23 Jan 2026 11:28:14 -0600 Subject: [PATCH] soc/intel/{mtl,ptl}/fsp_params: Program PcieRpSlotImplemented MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ADL programs this but MTL and PTL do not, so add it to the latter two for consistency. Change-Id: I8c982fcc810b3783cba4c66754df2b555bce6dfc Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/90878 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Sean Rhodes Reviewed-by: Angel Pons --- src/soc/intel/meteorlake/fsp_params.c | 3 +++ src/soc/intel/pantherlake/fsp_params.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 5e7bdc53ab..b3dfaffa5d 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -641,6 +641,9 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); + /* PcieRpSlotImplemented defaults to 1 (slot implemented) in FSP; 0: built-in */ + if (rp_cfg->flags & PCIE_RP_BUILT_IN) + s_cfg->PcieRpSlotImplemented[i] = false; s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; configure_pch_rp_power_management(s_cfg, rp_cfg, i); } diff --git a/src/soc/intel/pantherlake/fsp_params.c b/src/soc/intel/pantherlake/fsp_params.c index 226ae1677a..e5fb896513 100644 --- a/src/soc/intel/pantherlake/fsp_params.c +++ b/src/soc/intel/pantherlake/fsp_params.c @@ -601,6 +601,9 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG) || CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); + /* PcieRpSlotImplemented defaults to 1 (slot implemented) in FSP; 0: built-in */ + if (rp_cfg->flags & PCIE_RP_BUILT_IN) + s_cfg->PcieRpSlotImplemented[i] = false; s_cfg->PcieRpDetectTimeoutMs[i] = rp_cfg->pcie_rp_detect_timeout_ms; configure_pch_rp_power_management(s_cfg, rp_cfg, i); }