From ae2e78ce31714c2a3f3f6a4e03b9c7ae79dc76d7 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 15 Feb 2026 22:29:44 +0530 Subject: [PATCH] mb/google/fatcat/var/moonstone: Configure CDCLK frequency for display Configure the Core Display Clock (CDCLK) frequency selection by setting the 'vga_cd_clk_freq_sel' register to 1 in the moonstone variant overridetree. This ensures the display engine operates at the required frequency (442Mhz) for the panel to meet the hardware configuration. BUG=b:484559627 TEST=Build and boot google/moonstone, verify display initialization. Change-Id: I4d3d0082f9f221333150bd5b427b3f20e7a2f154 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/91236 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) --- src/mainboard/google/fatcat/variants/moonstone/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb index 7faed6236c..28b2fec984 100644 --- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb @@ -87,6 +87,8 @@ chip soc/intel/pantherlake register "cnvi_wifi_core" = "true" register "cnvi_bt_core" = "true" + register "vga_cd_clk_freq_sel" = "CD_CLK_442MHZ" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoDisabled,