diff --git a/src/mainboard/amd/birman/board_glinda.fmd b/src/mainboard/amd/birman/board_glinda.fmd
index 756709044e..bc09fe75d5 100644
--- a/src/mainboard/amd/birman/board_glinda.fmd
+++ b/src/mainboard/amd/birman/board_glinda.fmd
@@ -4,6 +4,6 @@ FLASH@0xFF000000 16M {
 		FMAP 4K
 		COREBOOT(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE 120K
+		RW_MRC_CACHE 256K
 	}
 }
diff --git a/src/mainboard/amd/birman/chromeos_glinda.fmd b/src/mainboard/amd/birman/chromeos_glinda.fmd
index 66227c2778..420ed6e6d4 100644
--- a/src/mainboard/amd/birman/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman/chromeos_glinda.fmd
@@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
 		SMMSTORE(PRESERVE) 256K
 		RW_LEGACY(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE(PRESERVE) 120K
+		RW_MRC_CACHE(PRESERVE) 256K
 	}
 }
diff --git a/src/mainboard/amd/birman_plus/board_glinda.fmd b/src/mainboard/amd/birman_plus/board_glinda.fmd
index b9465768be..96e1e8d8f0 100644
--- a/src/mainboard/amd/birman_plus/board_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/board_glinda.fmd
@@ -5,6 +5,6 @@ FLASH 64M {
 		COREBOOT(CBFS)
 		SMMSTORE(PRESERVE) 256K
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE 120K
+		RW_MRC_CACHE 256K
 	}
 }
diff --git a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
index 66227c2778..420ed6e6d4 100644
--- a/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
+++ b/src/mainboard/amd/birman_plus/chromeos_glinda.fmd
@@ -30,6 +30,6 @@ FLASH@0xFF000000 16M {
 		SMMSTORE(PRESERVE) 256K
 		RW_LEGACY(CBFS)
 		EC_BODY@15872K 256K
-		RW_MRC_CACHE(PRESERVE) 120K
+		RW_MRC_CACHE(PRESERVE) 256K
 	}
 }
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index 2e9381d57a..a02492cb8c 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -123,11 +123,11 @@ config PSP_APOB_DRAM_ADDRESS
 
 config PSP_APOB_DRAM_SIZE
 	hex
-	default 0x1E000
+	default 0x40000
 
 config PSP_SHAREDMEM_BASE
 	hex
-	default 0x201F000 if VBOOT
+	default 0x2041000 if VBOOT
 	default 0x0
 	help
 	  This variable defines the base address in DRAM memory where PSP copies
@@ -172,7 +172,7 @@ config C_ENV_BOOTBLOCK_SIZE
 
 config ROMSTAGE_ADDR
 	hex
-	default 0x2050000
+	default 0x2070000
 	help
 	  Sets the address in DRAM where romstage should be loaded.
 
@@ -184,7 +184,7 @@ config ROMSTAGE_SIZE
 
 config FSP_M_ADDR
 	hex
-	default 0x20C0000
+	default 0x20E0000
 	help
 	  Sets the address in DRAM where FSP-M should be loaded. cbfstool
 	  performs relocation of FSP-M to this address.
@@ -204,7 +204,7 @@ config FSP_TEMP_RAM_SIZE
 config VERSTAGE_ADDR
 	hex
 	depends on VBOOT_SEPARATE_VERSTAGE
-	default 0x2180000
+	default 0x21A0000
 	help
 	  Sets the address in DRAM where verstage should be loaded if running
 	  as a separate stage on x86.