From a1761f24e9dfa77cfeacacd5721cc5017dba574c Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 14 Dec 2013 05:17:41 -0800 Subject: [PATCH] Revert "tegra124: Fix bloated ROM stage." This reverts commit 58ee4a7f634711ee091841bd6669022a24e60f43. The underlying problem has been fixed by: ARM: Define custom ELF headers for ARM. $ cbfstool /build/nyan/firmware/coreboot.rom printcoreboot.rom: 1024 kB, bootblocksize 83968, romsize 1048576, offset 0x18080 alignment: 64 bytes, architecture: arm Name Offset Type Size fallback/romstage 0x18080 stage 17556 fallback/coreboot_ram 0x1c580 stage 31509 config 0x24100 raw 2920 (empty) 0x24cc0 null 897752 BUG=None TEST=Built for nyan and verified that the ROM stage was less than 18KB instead of being 46KB. BRANCH=None Change-Id: I4727f1b3d96a27a6382363565ab3153cec559547 Signed-off-by: Gabe Black Reviewed-on: https://chromium-review.googlesource.com/180164 Reviewed-by: Hung-Te Lin Commit-Queue: Gabe Black Tested-by: Gabe Black --- src/soc/nvidia/tegra124/Kconfig | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 89e9ae2d78..23f48f2c0d 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -37,8 +37,8 @@ config BOOTBLOCK_CPU_INIT # +4000 (Coreboot) Stack. # 0x4000_E000 Valid for anything to be executed after BootROM (effective entry # point address specified in BCT). -# +0000 (Coreboot) Bootblock (max 40k). -# +A000 (Coreboot) ROM stage (max 32k). +# +0000 (Coreboot) Bootblock (max 36k). +# +9000 (Coreboot) ROM stage (max 36k). # 0x4002_0000 (Coreboot) Cache of CBFS. # 0x4003_FFFF End of iRAM. @@ -62,10 +62,9 @@ config BOOTBLOCK_BASE hex default 0x4000e000 -# Note ROMSTAGE_BASE must be aligned to 0x8000. config ROMSTAGE_BASE hex - default 0x40018000 + default 0x40017000 config RAMSTAGE_BASE hex