From 9f8e5ab661a9d7c00f20fa229c1ed6e48270a8d7 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 6 Jun 2025 12:04:09 -0500 Subject: [PATCH] soc/intel/cmn/block/aspm: Use separate option variable for CPU RP Since the default ASPM UPD value (and valid values) differ between CPU and PCH-attached root ports, add a new option variable for CPU-attached RPs so that they are not inadvertently set to an invalid value, leading ASPM to be disabled on those RPs. Change-Id: I66ec77a3774a96cfe11f5827f5ba711ec826b236 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/87980 Tested-by: build bot (Jenkins) Reviewed-by: Sean Rhodes --- src/soc/intel/common/block/aspm/aspm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/aspm/aspm.c b/src/soc/intel/common/block/aspm/aspm.c index 0a1196c569..595de84d0d 100644 --- a/src/soc/intel/common/block/aspm/aspm.c +++ b/src/soc/intel/common/block/aspm/aspm.c @@ -120,7 +120,7 @@ void configure_cpu_rp_power_management(FSP_S_CONFIG *s_cfg, s_cfg->CpuPcieClockGating[index] = pciexp_clk_pm; s_cfg->CpuPciePowerGating[index] = pciexp_clk_pm; s_cfg->CpuPcieRpAspm[index] = - aspm_control_to_upd(get_uint_option("pciexp_aspm", rp_cfg->pcie_rp_aspm), true); + aspm_control_to_upd(get_uint_option("pciexp_aspm_cpu", rp_cfg->pcie_rp_aspm), true); s_cfg->CpuPcieRpL1Substates[index] = l1ss_control_to_upd(get_uint_option("pciexp_l1ss", rp_cfg->PcieRpL1Substates)); }