diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 97c2ecca70..34c9baf544 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -396,6 +396,19 @@ config CONSOLE_CBMEM_BUFFER_SIZE
 	default 0x100000 if BUILDING_WITH_DEBUG_FSP
 	default 0x40000
 
+config CHIPSETINIT_CBFS_FILE
+	string
+	depends on HAVE_CHIPSETINIT_BINARY
+	default "chipsetinit.bin"
+	help
+	  Name of the Chipset Initialization binary on the CBFS
+
+config HAVE_CHIPSETINIT_BINARY
+	bool
+	default n
+	help
+	  Select this option if you want to load the Chipset Initialization binary
+
 config FSP_TYPE_IOT
 	bool
 	default n
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index bd6f1d548a..396ea53c5a 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -664,6 +664,22 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 	s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER);
 }
 
+#if CONFIG(HAVE_CHIPSETINIT_BINARY)
+static void fill_fsps_chipsetinit_params(FSP_S_CONFIG *s_cfg,
+		const struct soc_intel_alderlake_config *config)
+{
+	void *data;
+	size_t size;
+
+	data = cbfs_map(CONFIG_CHIPSETINIT_CBFS_FILE, &size);
+	if (!data || size == 0)
+		return;
+
+	s_cfg->ChipsetInitBinPtr = (uint32_t)(uintptr_t)data;
+	s_cfg->ChipsetInitBinLen = (uint32_t)size;
+}
+#endif
+
 static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg,
 		const struct soc_intel_alderlake_config *config)
 {
@@ -1284,6 +1300,9 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		fill_fsps_cpu_params,
 		fill_fsps_igd_params,
 		fill_fsps_tcss_params,
+#if CONFIG(HAVE_CHIPSETINIT_BINARY)
+		fill_fsps_chipsetinit_params,
+#endif
 		fill_fsps_chipset_lockdown_params,
 		fill_fsps_xhci_params,
 		fill_fsps_xdci_params,