From 9f4132712f2ab22011837a4cc5c4f26a4ba9ddb3 Mon Sep 17 00:00:00 2001 From: Jamie Chen Date: Tue, 6 Jan 2026 16:20:57 +0800 Subject: [PATCH] soc/intel/alderlake: add chipsetinit support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Intel chipsetinit.bin is for PCH modphy initialize. Add code to read chipsetinit.bin from CBFS and fill UPD params. BUG=b:447290550 TEST=1. build coreboot 2. check log to confirm load chipsetinit.bin successfully. Change-Id: I65740f52c779daeea1a27a9e078336daee29cf3b Signed-off-by: Jamie Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/90687 Reviewed-by: Simon Yang Tested-by: build bot (Jenkins) Reviewed-by: Kao, Ben Reviewed-by: Jérémy Compostella --- src/soc/intel/alderlake/Kconfig | 13 +++++++++++++ src/soc/intel/alderlake/fsp_params.c | 19 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 97c2ecca70..34c9baf544 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -396,6 +396,19 @@ config CONSOLE_CBMEM_BUFFER_SIZE default 0x100000 if BUILDING_WITH_DEBUG_FSP default 0x40000 +config CHIPSETINIT_CBFS_FILE + string + depends on HAVE_CHIPSETINIT_BINARY + default "chipsetinit.bin" + help + Name of the Chipset Initialization binary on the CBFS + +config HAVE_CHIPSETINIT_BINARY + bool + default n + help + Select this option if you want to load the Chipset Initialization binary + config FSP_TYPE_IOT bool default n diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index bd6f1d548a..396ea53c5a 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -664,6 +664,22 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER); } +#if CONFIG(HAVE_CHIPSETINIT_BINARY) +static void fill_fsps_chipsetinit_params(FSP_S_CONFIG *s_cfg, + const struct soc_intel_alderlake_config *config) +{ + void *data; + size_t size; + + data = cbfs_map(CONFIG_CHIPSETINIT_CBFS_FILE, &size); + if (!data || size == 0) + return; + + s_cfg->ChipsetInitBinPtr = (uint32_t)(uintptr_t)data; + s_cfg->ChipsetInitBinLen = (uint32_t)size; +} +#endif + static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, const struct soc_intel_alderlake_config *config) { @@ -1284,6 +1300,9 @@ static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, fill_fsps_cpu_params, fill_fsps_igd_params, fill_fsps_tcss_params, +#if CONFIG(HAVE_CHIPSETINIT_BINARY) + fill_fsps_chipsetinit_params, +#endif fill_fsps_chipset_lockdown_params, fill_fsps_xhci_params, fill_fsps_xdci_params,