diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c
index c98ce102b4..4a03b7438f 100644
--- a/src/soc/intel/alderlake/romstage/fsp_params.c
+++ b/src/soc/intel/alderlake/romstage/fsp_params.c
@@ -439,13 +439,15 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
 	 * packed as part of the CBFS then CSE sync will be triggered. CSE sync can take
 	 * < 1-minute hence, let's inform the end user with an on-screen text message.
 	 */
-	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()) {
+	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()
+		&& !is_cse_boot_to_rw()) {
 		if (esol_required) {
 			name = "memory training and CSE update";
 		} else {
 			name = "CSE update";
 			esol_required =  true;
 		}
+		elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
 	}
 
 	if (esol_required)
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index d3a2884018..daf2b76ae6 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -208,8 +208,10 @@ void mainboard_romstage_entry(void)
 	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) {
 		cse_fill_bp_info();
 		if (CONFIG(CHROMEOS_ENABLE_ESOL) &&
-		    is_cse_fw_update_required() && !is_cse_boot_to_rw())
+		    is_cse_fw_update_required() && !is_cse_boot_to_rw()) {
+			elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
 			ux_inform_user_of_update_operation("CSE update");
+		}
 		cse_fw_sync();
 	}
 
diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c
index 76e0853637..07233a9fb5 100644
--- a/src/soc/intel/common/block/cse/cse_lite.c
+++ b/src/soc/intel/common/block/cse/cse_lite.c
@@ -806,7 +806,6 @@ static enum cb_err cse_write_rw_region(const struct region_device *target_rdev,
 		return CB_ERR;
 
 	printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n");
-	elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
 	return CB_SUCCESS;
 }
 
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index bc7c20b8bc..82706ed3bf 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -456,8 +456,11 @@ static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg,
 		elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC);
 	}
 
-	if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required())
+	if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()
+		&& !is_cse_boot_to_rw()) {
 		vga_init_control = VGA_INIT_CONTROL_ENABLE;
+		elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC);
+	}
 
 	if (!vga_init_control)
 		return;