From 993ac31838cdf9eb8d6abfdd855f6abc741c54c8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 13 Jun 2017 14:17:05 +0200 Subject: [PATCH] UPSTREAM: soc/intel/skylake: Don't allow user to change DCACHE base and size BUG=none BRANCH=none TEST=none Change-Id: I584088ba0b02411b8c59c6a5d84d1aa27bfd883f Signed-off-by: Patrick Georgi Original-Commit-Id: 432ac615d018465e9808be4286c0caf2ca192cf1 Original-Change-Id: Ic1656311ecc670dc0436995f0ec8199d270da4d1 Original-Signed-off-by: Arthur Heymans Original-Reviewed-on: https://review.coreboot.org/20180 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin Original-Reviewed-by: Philippe Mathieu-Daud Original-Reviewed-by: Sumeet R Pawnikar Reviewed-on: https://chromium-review.googlesource.com/539216 Commit-Ready: Patrick Georgi Tested-by: Patrick Georgi Reviewed-by: Patrick Georgi --- src/soc/intel/skylake/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 26f90218d7..fb2d94b974 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -127,11 +127,11 @@ config CPU_ADDR_BITS default 36 config DCACHE_RAM_BASE - hex "Base address of cache-as-RAM" + hex default 0xfef00000 config DCACHE_RAM_SIZE - hex "Length in bytes of cache-as-RAM" + hex default 0x40000 help The size of the cache-as-ram region required during bootblock