From 993a9c9e14ab9a6ca5dd70e43a7c93dbe1f91ed9 Mon Sep 17 00:00:00 2001 From: Kilian Krause Date: Wed, 11 Jun 2025 12:26:24 +0200 Subject: [PATCH] mb/siemens/mc_rpl1: Configure SATA Ports This board does only use SATA Port 0 and SATA Port 1. The rest is disabled. In addition, power management features like DevSlp and Aggressive Link Power management are not supported on this motherboard and are deactivated accordingly. TEST=Verified SATA config: `dmesg | grep -i "sata link"` shows ports 0-1 active at 3.0 Gbps (Gen2 limit). Change-Id: I4567328c25f195fac8edc02518a6a812922f48e5 Signed-off-by: Kilian Krause Reviewed-on: https://review.coreboot.org/c/coreboot/+/88952 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer Reviewed-by: Paul Menzel --- src/mainboard/siemens/mc_rpl/devicetree.cb | 17 ----------------- .../mc_rpl/variants/mc_rpl1/overridetree.cb | 9 +++++++++ 2 files changed, 9 insertions(+), 17 deletions(-) diff --git a/src/mainboard/siemens/mc_rpl/devicetree.cb b/src/mainboard/siemens/mc_rpl/devicetree.cb index a5af508a2f..fdd62466aa 100644 --- a/src/mainboard/siemens/mc_rpl/devicetree.cb +++ b/src/mainboard/siemens/mc_rpl/devicetree.cb @@ -13,22 +13,6 @@ chip soc/intel/alderlake # Sagv Configuration register "sagv" = "SaGv_Enabled" - register "sata_salp_support" = "1" - - register "sata_ports_enable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" - - register "sata_ports_dev_slp" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" - register "s0ix_enable" = "true" register "dptf_enable" = "true" @@ -130,7 +114,6 @@ chip soc/intel/alderlake end end device ref crashlog off end - device ref sata on end device ref p2sb on end device ref smbus on end end diff --git a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb index b6ba91a40d..9e8da22920 100644 --- a/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb +++ b/src/mainboard/siemens/mc_rpl/variants/mc_rpl1/overridetree.cb @@ -3,6 +3,14 @@ chip soc/intel/alderlake # seen on J0 and Q0 SKUs register "disable_package_c_state_demotion" = "true" + register "sata_salp_support" = "0" + register "sata_speed" = "SATA_GEN2" + + register "sata_ports_enable" = "{ + [0] = 1, + [1] = 1, + }" + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Port1 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Port2 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Onboard USB @@ -128,5 +136,6 @@ chip soc/intel/alderlake device pnp 0c31.0 on end end end + device ref sata on end end end