From 958099b11422caed6ccf4043bd57799b55ac480d Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 18 Nov 2025 16:49:37 +0000 Subject: [PATCH] soc/qualcomm: Map the post-RAM DMA coherent buffer The MMU configuration in qc_mmu_dram_config_post_dram_init() needs to include the memory region allocated for DMA coherent buffers. Map the `postram_dma_coherent` region as UNCACHED_RAM to ensure memory writes bypass the CPU cache hierarchy. The mapping is only configured if the `_postram_dma_coherent` address is different from `_preram_dma_coherent` address aka migration of the region. This is necessary for DMA operations that occur after DRAM is initialized. BUG=b:456953373 TEST=Able to build google/quenbi. Change-Id: If5f625ad74f4f6ea244c8b377543be3666122cea Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/90050 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Kapil Porwal --- src/soc/qualcomm/common/mmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/qualcomm/common/mmu.c b/src/soc/qualcomm/common/mmu.c index ff8d5dc98e..b589d966a9 100644 --- a/src/soc/qualcomm/common/mmu.c +++ b/src/soc/qualcomm/common/mmu.c @@ -73,4 +73,7 @@ void qc_mmu_dram_config_post_dram_init(size_t ddr_size) CACHED_RAM); mmu_config_range((void *)_aop_data_ram, REGION_SIZE(aop_data_ram), CACHED_RAM); + if (_preram_dma_coherent != _postram_dma_coherent) + mmu_config_range((void *)_postram_dma_coherent, REGION_SIZE(postram_dma_coherent), + UNCACHED_RAM); }