diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld
index 664ef3570c..0e44bd6e8b 100644
--- a/src/soc/qualcomm/x1p42100/memlayout.ld
+++ b/src/soc/qualcomm/x1p42100/memlayout.ld
@@ -57,7 +57,8 @@ SECTIONS
 	REGION(shrm, 0x24040000, 128K , 4K)
 
 	DRAM_START(0x80000000)
+	REGION(dram_aop, 0x81c00000, 0x0a0000, 0x1000)
 	POSTRAM_CBFS_CACHE(0x9F800000, 16M)
 	RAMSTAGE(0xA0800000, 16M)
-	BL31(0xC0000000, 1M)
+	BL31(0xD80D6000, 1M)
 }
diff --git a/src/soc/qualcomm/x1p42100/soc.c b/src/soc/qualcomm/x1p42100/soc.c
index f43d348684..0dd4a4035b 100644
--- a/src/soc/qualcomm/x1p42100/soc.c
+++ b/src/soc/qualcomm/x1p42100/soc.c
@@ -1,6 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <device/device.h>
+#include <soc/mmu.h>
+#include <soc/mmu_common.h>
 #include <soc/symbols_common.h>
 #include <soc/pcie.h>
 
@@ -12,7 +14,8 @@ static struct device_operations pci_domain_ops = {
 };
 static void soc_read_resources(struct device *dev)
 {
-	/* placeholder */
+	ram_range(dev, 0, (uintptr_t)region_offset(ddr_region), region_sz(ddr_region));
+	reserved_ram_range(dev, 1, (uintptr_t)_dram_aop, REGION_SIZE(dram_aop));
 }
 
 static void soc_init(struct device *dev)