diff --git a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
index ffe692d282..0095aa5d13 100644
--- a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
+++ b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl
@@ -32,8 +32,10 @@
 		Method (_OSC, 4, NotSerialized)				\
 		{							\
 			Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3,	\
-				(PCIE_CAP_STRUCTURE_CONTROL|		\
+				(PCIE_LTR_CONTROL|			\
+				PCIE_CAP_STRUCTURE_CONTROL|		\
 				PCIE_PME_CONTROL|			\
+				PCIE_AER_CONTROL|			\
 				PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0))	\
 		}							\
 	}
diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
index bf027663e0..3ff3635247 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
@@ -39,8 +39,10 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK))
 	Method (_OSC, 4, NotSerialized)
 	{
 		Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3,
-			(PCIE_CAP_STRUCTURE_CONTROL|
+			(PCIE_LTR_CONTROL|
+			PCIE_CAP_STRUCTURE_CONTROL|
 			PCIE_PME_CONTROL|
+			PCIE_AER_CONTROL|
 			PCIE_NATIVE_HOTPLUG_CONTROL), 1,
 			CXL_ERROR_REPORTING_CONTROL))
 	}
diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
index a81f28a595..83a6efa88d 100644
--- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
+++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
@@ -37,8 +37,10 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK))
 	Method (_OSC, 4, NotSerialized)
 	{
 		Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3,
-			(PCIE_CAP_STRUCTURE_CONTROL|
+			(PCIE_LTR_CONTROL|
+			PCIE_CAP_STRUCTURE_CONTROL|
 			PCIE_PME_CONTROL|
+			PCIE_AER_CONTROL|
 			PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0))
 	}
 }