From 90196f530fc379f4447f12949122cd60a411d3b0 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 11 Dec 2024 12:12:40 +0100 Subject: [PATCH] soc/intel/xeon_sp: Allow OS to control LTR and AER There's no reason to tell the OS to disable LTR. On UEFI and on coreboot's GNR LTR is allowed, thus allow it for all Xeon-SP. There's no SMM (RAS) code that is able to parse AER structures, thus let the OS always control AER. On coreboot's GNR AER is also always granted to the OS. TEST: Run code on ocp/tiogapass and observed dmesg: The OS now prints: acpi PNP0A08:04: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability LTR] Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/85561 Reviewed-by: Shuo Liu Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) Reviewed-by: Marvin Drees --- src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl | 4 +++- src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl | 4 +++- src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl | 4 +++- 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl index ffe692d282..0095aa5d13 100644 --- a/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl +++ b/src/soc/intel/xeon_sp/acpi/gen1/iiostack.asl @@ -32,8 +32,10 @@ Method (_OSC, 4, NotSerialized) \ { \ Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, \ - (PCIE_CAP_STRUCTURE_CONTROL| \ + (PCIE_LTR_CONTROL| \ + PCIE_CAP_STRUCTURE_CONTROL| \ PCIE_PME_CONTROL| \ + PCIE_AER_CONTROL| \ PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0)) \ } \ } diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index bf027663e0..3ff3635247 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -39,8 +39,10 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK)) Method (_OSC, 4, NotSerialized) { Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, - (PCIE_CAP_STRUCTURE_CONTROL| + (PCIE_LTR_CONTROL| + PCIE_CAP_STRUCTURE_CONTROL| PCIE_PME_CONTROL| + PCIE_AER_CONTROL| PCIE_NATIVE_HOTPLUG_CONTROL), 1, CXL_ERROR_REPORTING_CONTROL)) } diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index a81f28a595..83a6efa88d 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -37,8 +37,10 @@ Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET_NAME, STACK)) Method (_OSC, 4, NotSerialized) { Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, - (PCIE_CAP_STRUCTURE_CONTROL| + (PCIE_LTR_CONTROL| + PCIE_CAP_STRUCTURE_CONTROL| PCIE_PME_CONTROL| + PCIE_AER_CONTROL| PCIE_NATIVE_HOTPLUG_CONTROL), 0 , 0)) } }