diff --git a/src/soc/intel/common/block/cpu/smmrelocate.c b/src/soc/intel/common/block/cpu/smmrelocate.c
index 8c45c218b2..e510c96f99 100644
--- a/src/soc/intel/common/block/cpu/smmrelocate.c
+++ b/src/soc/intel/common/block/cpu/smmrelocate.c
@@ -78,6 +78,15 @@ static int bsp_setup_msr_save_state(struct smm_relocation_params *relo_params)
 {
 	msr_t smm_mca_cap;
 
+	/*
+	 * FIXME: On Xeon-SP the MSR SMM_FEATURE_CONTROL_MSR is not implemented.
+	 *        SMM feature control resides on the UBOX PCI device.
+	 * FIXME: Need to enable save state in MSRs on all sockets, however BSP
+	 *        runs on a single socket only.
+	 */
+	if (CONFIG(XEON_SP_COMMON_BASE) || CONFIG(SOC_INTEL_SNOWRIDGE))
+		return 0;
+
 	smm_mca_cap = rdmsr(SMM_MCA_CAP_MSR);
 	if (smm_mca_cap.hi & SMM_CPU_SVRSTR_MASK) {
 		msr_t smm_feature_control;
diff --git a/src/soc/intel/snowridge/include/soc/msr.h b/src/soc/intel/snowridge/include/soc/msr.h
index b45050b794..45bf831290 100644
--- a/src/soc/intel/snowridge/include/soc/msr.h
+++ b/src/soc/intel/snowridge/include/soc/msr.h
@@ -5,14 +5,6 @@
 
 #include <intelblocks/msr.h>
 
-/**
- * @brief Force serialized SMM relocation by hardcoding `SMM_CPU_SVRSTR` feature as not supported.
- */
-#ifdef SMM_CPU_SVRSTR_MASK
-#undef SMM_CPU_SVRSTR_MASK
-#endif
-#define SMM_CPU_SVRSTR_MASK 0
-
 #define MSR_BIOS_DONE       0x151
 #define ENABLE_IA_UNTRUSTED BIT(0)