From 861413b2951fe3ab01f34ec12ec32631aaa66d95 Mon Sep 17 00:00:00 2001 From: David Wu Date: Fri, 6 Dec 2024 15:41:12 +0800 Subject: [PATCH] mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2 The issue does not occur on Karis due to different WIFI module type with current projects, Karis is using M.2 (none solder down version). The decision to set PCIe root port 4 speed to Gen2 is based on experiment setup for b/374205496 and analysis results in #102. BUG=b:374205496 TEST=Boot to OS and then check link speed. Use command: lspci -vv | grep 'LnkSta' Before LnkSta: Speed 8GT/s (downgraded), Width x1 After LnkSta: Speed 5GT/s (downgraded), Width x1 Change-Id: Ife2b60e78f943545fabd7095bd00d22704587aba Signed-off-by: David Wu Reviewed-on: https://review.coreboot.org/c/coreboot/+/85520 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/mainboard/google/brya/variants/riven/overridetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/brya/variants/riven/overridetree.cb b/src/mainboard/google/brya/variants/riven/overridetree.cb index 9f62d2763c..136bf1c409 100644 --- a/src/mainboard/google/brya/variants/riven/overridetree.cb +++ b/src/mainboard/google/brya/variants/riven/overridetree.cb @@ -487,6 +487,7 @@ chip soc/intel/alderlake .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_pcie_speed = SPEED_GEN2, }" chip drivers/wifi/generic register "wake" = "GPE0_DW1_03"