From 85b26f75d2174afd648fc8a6df17679e770f6f5d Mon Sep 17 00:00:00 2001 From: Jincheng Li Date: Mon, 21 Jul 2025 18:16:12 +0800 Subject: [PATCH] soc/intel/xeon_sp: Remove fast_spi_cache_bios_region FSP-T will help to cache bios region along with MTRR programming by setting CodeRegionBase/CodeRegionLength, thus there is no need for xeon_sp platforms to do it. TEST=Build and boot on intel/avenuecity CRB TEST=Build and boot on intel/archercity CRB Check MTRR usage and below duplicated MTRR item get removed: [DEBUG] 0x00000000ff000005: PHYBASE1: Address = 0x00000000ff000000, WP [DEBUG] 0x000fffffff000800: PHYMASK1: Length = 0x0000000001000000, Valid Change-Id: Ia414a35c663f3aa1b02d944475a96e11d07a4f00 Signed-off-by: Jincheng Li Reviewed-on: https://review.coreboot.org/c/coreboot/+/88533 Tested-by: build bot (Jenkins) Reviewed-by: Shuo Liu --- src/soc/intel/xeon_sp/bootblock.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 49548ed9ef..1e9c3bbc62 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -73,14 +73,13 @@ asmlinkage void bootblock_c_entry(uint64_t base_timestamp) */ assembly_timestamp = base_timestamp; bootblock_timestamp = timestamp_get(); - fast_spi_early_init(SPI_BASE_ADDRESS); - fast_spi_cache_bios_region(); bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp)); } void bootblock_soc_early_init(void) { + fast_spi_early_init(SPI_BASE_ADDRESS); pch_enable_lpc(); /* Set up P2SB BAR. This is needed for PCR to work */