From 84899e6fb76f087f3dc5c50bfda6d70c42b40e6f Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 13 Jul 2025 19:03:47 +0200 Subject: [PATCH] sb/intel: Convert set_gpio to gpio_set Drop the custom function to set the value of a single GPIO and use the generic function prototype defined in include/gpio.h instead. Migrate all users of the old function to the new function. Allows to share more code between older x86 Intel boards and newer x86 Intel boards since they now use a common header. Change-Id: I8c83b3436818275958cd8eb8b1c0d7b235e0344c Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/88504 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- .../lenovo/hybrid_graphics/hybrid_graphics.c | 9 ++++----- src/drivers/lenovo/hybrid_graphics/romstage.c | 5 ++--- .../variants/p8z77-v_le_plus/early_init.c | 4 ++-- src/mainboard/google/auron/smihandler.c | 11 ++++++----- .../google/auron/variants/samus/variant.c | 8 ++++---- src/mainboard/google/jecht/smihandler.c | 3 ++- src/mainboard/google/slippy/smihandler.c | 16 ++++++++-------- src/mainboard/lenovo/t400/romstage.c | 3 +-- src/mainboard/lenovo/x200/romstage.c | 4 ++-- src/mainboard/lenovo/x200/variants/x200/dock.c | 5 ++--- src/mainboard/lenovo/x201/dock.c | 7 +++---- src/southbridge/intel/common/gpio.c | 2 +- src/southbridge/intel/common/gpio.h | 2 -- src/southbridge/intel/lynxpoint/lp_gpio.c | 2 +- src/southbridge/intel/lynxpoint/lp_gpio.h | 3 --- 15 files changed, 38 insertions(+), 46 deletions(-) diff --git a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c index ebd7efccac..1d960f7f06 100644 --- a/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c +++ b/src/drivers/lenovo/hybrid_graphics/hybrid_graphics.c @@ -4,7 +4,6 @@ #include #include #include -#include #include "chip.h" /* @@ -32,22 +31,22 @@ static void lenovo_hybrid_graphics_enable(struct device *dev) " Switching panel to discrete GPU.\n"); if (config->has_panel_hybrid_gpio) - set_gpio(config->panel_hybrid_gpio, + gpio_set(config->panel_hybrid_gpio, !config->panel_integrated_lvl); if (config->has_backlight_gpio) - set_gpio(config->backlight_gpio, + gpio_set(config->backlight_gpio, !config->backlight_integrated_lvl); } else { printk(BIOS_DEBUG, "Hybrid graphics:" " Switching panel to integrated GPU.\n"); if (config->has_panel_hybrid_gpio) - set_gpio(config->panel_hybrid_gpio, + gpio_set(config->panel_hybrid_gpio, config->panel_integrated_lvl); if (config->has_backlight_gpio) - set_gpio(config->backlight_gpio, + gpio_set(config->backlight_gpio, config->backlight_integrated_lvl); } } diff --git a/src/drivers/lenovo/hybrid_graphics/romstage.c b/src/drivers/lenovo/hybrid_graphics/romstage.c index b28237c8c3..10f94439f8 100644 --- a/src/drivers/lenovo/hybrid_graphics/romstage.c +++ b/src/drivers/lenovo/hybrid_graphics/romstage.c @@ -6,7 +6,6 @@ #include #include #include -#include #include "hybrid_graphics.h" #include "chip.h" @@ -67,10 +66,10 @@ void early_hybrid_graphics(bool *enable_igd, bool *enable_peg) */ if (config->has_dgpu_power_gpio) { if (*enable_peg) - set_gpio(config->dgpu_power_gpio, + gpio_set(config->dgpu_power_gpio, !config->dgpu_power_off_lvl); else - set_gpio(config->dgpu_power_gpio, + gpio_set(config->dgpu_power_gpio, config->dgpu_power_off_lvl); } else if (config->has_thinker1) { bool power_en = pmh7_dgpu_power_state(); diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c index 024f8e9d81..343c9a889b 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_le_plus/early_init.c @@ -5,10 +5,10 @@ #include #include #include +#include #include #include #include -#include #include #include #include @@ -85,7 +85,7 @@ void bootblock_mainboard_init(void) } /* Match GPIO to soft strap. */ - set_gpio(46, gp46); + gpio_set(46, gp46); } void bootblock_mainboard_early_init(void) diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c index e20976c5f1..9485b8d13a 100644 --- a/src/mainboard/google/auron/smihandler.c +++ b/src/mainboard/google/auron/smihandler.c @@ -2,11 +2,12 @@ #include #include -#include #include #include +#include #include #include +#include #include "ec.h" #include @@ -21,14 +22,14 @@ static void mainboard_disable_gpios(void) { #if CONFIG(BOARD_GOOGLE_SAMUS) /* Put SSD in reset to prevent leak */ - set_gpio(BOARD_SSD_RESET_GPIO, 0); + gpio_set(BOARD_SSD_RESET_GPIO, 0); /* Disable LTE */ - set_gpio(BOARD_LTE_DISABLE_GPIO, 0); + gpio_set(BOARD_LTE_DISABLE_GPIO, 0); #else - set_gpio(BOARD_PP3300_CODEC_GPIO, 0); + gpio_set(BOARD_PP3300_CODEC_GPIO, 0); #endif /* Prevent leak from standby rail to WLAN rail */ - set_gpio(BOARD_WLAN_DISABLE_GPIO, 0); + gpio_set(BOARD_WLAN_DISABLE_GPIO, 0); } void mainboard_smi_sleep(u8 slp_typ) diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c index 441cefe6e8..23468aba1e 100644 --- a/src/mainboard/google/auron/variants/samus/variant.c +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -2,13 +2,13 @@ #include #include -#include +#include +#include #include #include #include #include #include -#include const char *smbios_mainboard_version(void) { @@ -29,11 +29,11 @@ void mainboard_post_raminit(const int s3resume) printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version()); /* Bring SSD out of reset */ - set_gpio(BOARD_SSD_RESET_GPIO, 1); + gpio_set(BOARD_SSD_RESET_GPIO, 1); /* * Enable PP3300_AUTOBAHN_EN after initial GPIO setup * to prevent possible brownout. */ - set_gpio(BOARD_PP3300_AUTOBAHN_GPIO, 1); + gpio_set(BOARD_PP3300_AUTOBAHN_GPIO, 1); } diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 076d3fe08c..7743ce546e 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -21,7 +22,7 @@ void mainboard_smi_sleep(u8 slp_typ) /* Enable DCP mode */ if (CONFIG(BOARD_GOOGLE_TIDUS)) { - set_gpio(GPIO_USB_CTL_1, 0); + gpio_set(GPIO_USB_CTL_1, 0); } break; case ACPI_S5: diff --git a/src/mainboard/google/slippy/smihandler.c b/src/mainboard/google/slippy/smihandler.c index cefaf7a099..42e79220e1 100644 --- a/src/mainboard/google/slippy/smihandler.c +++ b/src/mainboard/google/slippy/smihandler.c @@ -1,12 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include -#include -#include -#include #include +#include +#include +#include +#include +#include /* Include EC functions */ #include @@ -35,10 +35,10 @@ void mainboard_smi_sleep(u8 slp_typ) case ACPI_S4: case ACPI_S5: /* Prevent leak from standby rail to WLAN rail in S3/S4/S5. */ - set_gpio(GPIO_WLAN_DISABLE_L, 0); - set_gpio(GPIO_PP3300_CODEC_EN, 0); + gpio_set(GPIO_WLAN_DISABLE_L, 0); + gpio_set(GPIO_PP3300_CODEC_EN, 0); /* Disable LTE */ - set_gpio(GPIO_LTE_DISABLE_L, 0); + gpio_set(GPIO_LTE_DISABLE_L, 0); break; } diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 850116aad2..20add1e112 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -4,7 +4,6 @@ #include #include #include -#include static void hybrid_graphics_init(sysinfo_t *sysinfo) { @@ -44,5 +43,5 @@ void mb_post_raminit_setup(void) { /* FIXME: make a proper SMBUS mux support. */ /* Set the SMBUS mux to the eeprom */ - set_gpio(42, GPIO_LEVEL_LOW); + gpio_set(42, GPIO_LEVEL_LOW); } diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 6764644274..224c46b865 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include +#include #include void get_mb_spd_addrmap(u8 spd_addrmap[4]) @@ -13,5 +13,5 @@ void mb_post_raminit_setup(void) { /* FIXME: make a proper SMBUS mux support. */ /* Set the SMBUS mux to the eeprom */ - set_gpio(42, GPIO_LEVEL_LOW); + gpio_set(42, GPIO_LEVEL_LOW); } diff --git a/src/mainboard/lenovo/x200/variants/x200/dock.c b/src/mainboard/lenovo/x200/variants/x200/dock.c index a10772ede2..da085dc7aa 100644 --- a/src/mainboard/lenovo/x200/variants/x200/dock.c +++ b/src/mainboard/lenovo/x200/variants/x200/dock.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include @@ -22,13 +21,13 @@ void h8_mb_init(void) void dock_connect(void) { ec_set_bit(0x02, 0); - set_gpio(28, GPIO_LEVEL_HIGH); + gpio_set(28, GPIO_LEVEL_HIGH); } void dock_disconnect(void) { ec_clr_bit(0x02, 0); - set_gpio(28, GPIO_LEVEL_LOW); + gpio_set(28, GPIO_LEVEL_LOW); } int dock_present(void) diff --git a/src/mainboard/lenovo/x201/dock.c b/src/mainboard/lenovo/x201/dock.c index a1bd1e81d7..202fc26f07 100644 --- a/src/mainboard/lenovo/x201/dock.c +++ b/src/mainboard/lenovo/x201/dock.c @@ -3,10 +3,9 @@ #include #include #include -#include "dock.h" -#include #include #include +#include "dock.h" void h8_mb_init(void) { @@ -24,7 +23,7 @@ void dock_connect(void) ec_set_bit(0x1a, 0); ec_set_bit(0xfe, 4); - set_gpio(28, GPIO_LEVEL_HIGH); + gpio_set(28, GPIO_LEVEL_HIGH); } void dock_disconnect(void) @@ -33,7 +32,7 @@ void dock_disconnect(void) ec_clr_bit(0x1a, 0); ec_clr_bit(0xfe, 4); - set_gpio(28, GPIO_LEVEL_LOW); + gpio_set(28, GPIO_LEVEL_LOW); } int dock_present(void) diff --git a/src/southbridge/intel/common/gpio.c b/src/southbridge/intel/common/gpio.c index a033ead057..8ce77fbcb6 100644 --- a/src/southbridge/intel/common/gpio.c +++ b/src/southbridge/intel/common/gpio.c @@ -105,7 +105,7 @@ int gpio_get(gpio_t gpio_num) /* * set gpio output to level. */ -void set_gpio(int gpio_num, int value) +void gpio_set(gpio_t gpio_num, int value) { static const int gpio_reg_offsets[] = { GP_LVL, GP_LVL2, GP_LVL3 diff --git a/src/southbridge/intel/common/gpio.h b/src/southbridge/intel/common/gpio.h index 4e47f18ae2..8c7b2301ac 100644 --- a/src/southbridge/intel/common/gpio.h +++ b/src/southbridge/intel/common/gpio.h @@ -151,8 +151,6 @@ extern const struct pch_gpio_map mainboard_gpio_map; /* Configure GPIOs with mainboard provided settings */ void setup_pch_gpios(const struct pch_gpio_map *gpio); -void set_gpio(int gpio_num, int value); - void clear_gpio(int gpio_num); int gpio_is_native(int gpio_num); diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index 123e4a43f9..e5884e8d8d 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -110,7 +110,7 @@ int gpio_get(gpio_t gpio_num) return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL); } -void set_gpio(int gpio_num, int value) +void gpio_set(gpio_t gpio_num, int value) { u16 gpio_base = get_gpio_base(); u32 conf0; diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.h b/src/southbridge/intel/lynxpoint/lp_gpio.h index dd2a89a373..7c051b138b 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.h +++ b/src/southbridge/intel/lynxpoint/lp_gpio.h @@ -157,9 +157,6 @@ struct pch_lp_gpio_map { /* Configure GPIOs with mainboard provided settings */ void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]); -/* Set GPIO pin value */ -void set_gpio(int gpio_num, int value); - /* Return non-zero if gpio is set to native function. 0 otherwise. */ int gpio_is_native(int gpio_num);