diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index e47deb5da6..386c2897cc 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -8,7 +8,7 @@
 
 #include "haswell.h"
 
-static bool peg_hidden[3];
+static bool peg_hidden[MAX_PEG_FUNC];
 
 static void haswell_setup_bars(void)
 {
@@ -111,7 +111,7 @@ void haswell_unhide_peg(void)
 {
 	u32 deven = pci_read_config32(HOST_BRIDGE, DEVEN);
 
-	for (u8 fn = 0; fn <= 2; fn++) {
+	for (u8 fn = 0; fn < MAX_PEG_FUNC; fn++) {
 		if (peg_hidden[fn]) {
 			deven |= DEVEN_D1F0EN >> fn;
 			peg_hidden[fn] = false;
diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c
index 3fc8713d29..2b244c5a69 100644
--- a/src/northbridge/intel/haswell/early_pcie.c
+++ b/src/northbridge/intel/haswell/early_pcie.c
@@ -7,10 +7,6 @@
 #include <northbridge/intel/haswell/vcu_mailbox.h>
 #include <types.h>
 
-#define PEG_DEV(func)		PCI_DEV(0, 1, func)
-
-#define MAX_PEG_FUNC		3
-
 static void peg_dmi_unset_and_set_mask_pcicfg(
 	volatile union pci_bank *const bank,
 	const uint32_t offset,
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 30b4abd0a7..bd271f4b06 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -16,6 +16,11 @@
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
 #define HOST_BRIDGE	PCI_DEV(0, 0, 0)
 
+/* Device 0:1.x PCI configuration space (PCI Express Graphics) */
+#define PEG_DEV(func)		PCI_DEV(0, 1, func)
+
+#define MAX_PEG_FUNC		3
+
 /* Device 0:2.0 PCI configuration space (Graphics Device) */
 
 #define MSAC		0x62	/* Multi Size Aperture Control */