From 7493b41f37f7ba301212d18bdadd7e09df18d7c4 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Wed, 11 Feb 2026 13:33:24 +0100 Subject: [PATCH] mb/amd/birman_plus: Disable PCIe feature programming Before the PCIe features can be programmed FSP-S must set non public bits in the EnumInitPhaseAfterPciEnumeration callback. Violating this rule causes system instabilities and reboot loops, depending on the selected features and hardware plugged into slots. Since FSP-S can handle all types of PCIe features disable all of them in coreboot and let FSP set the bits at the right time. TEST=Can boot on AMD/glinda with ASPM L1SS enabled without seeing system crashed. Change-Id: Ib4c4597c91d6612018e4f55e1a989a676aff842d Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/91164 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/mainboard/amd/birman_plus/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/amd/birman_plus/Kconfig b/src/mainboard/amd/birman_plus/Kconfig index a5291a495c..21b8607b48 100644 --- a/src/mainboard/amd/birman_plus/Kconfig +++ b/src/mainboard/amd/birman_plus/Kconfig @@ -8,10 +8,6 @@ config BOARD_AMD_BIRMANPLUS_COMMON select DRIVERS_PCIE_RTD3_DEVICE select DRIVERS_I2C_GENERIC select MAINBOARD_HAS_CHROMEOS - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_COMMON_CLOCK - select PCIEXP_L1_SUB_STATE select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN if !SOC_AMD_COMMON_BLOCK_SIMNOW_BUILD select SOC_AMD_COMMON_BLOCK_SIMNOW_SUPPORTED select SPI_FLASH_EXIT_4_BYTE_ADDR_MODE