From 6dbcf903a599923bb8eff573fc10d26d3e4cfe77 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Tue, 18 Nov 2025 09:21:30 -0800 Subject: [PATCH] soc/intel/pantherlake: Add ICC Max and TDC settings for SKU_7 SKU_7 ICC Max and TDC were not accurate. This commit aligns SKU_7 settings with document #813278 - Panther Lake H Platform Power Map 2.1.1. Change-Id: Ia66ca5c0d2dc1ba0f0cf3b21476e83923e49969e Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/90096 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Subrata Banik --- src/soc/intel/pantherlake/chip.h | 3 ++- src/soc/intel/pantherlake/chipset_ptl.cb | 7 +++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index d6b3aff027..d383d63fa5 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -76,6 +76,7 @@ enum soc_intel_pantherlake_sku { PTL_SKU_4, PTL_SKU_5, PTL_SKU_6, + PTL_SKU_7, WCL_SKU_1, WCL_SKU_2, WCL_SKU_3, @@ -115,7 +116,7 @@ static const struct soc_intel_pantherlake_power_map { { PCI_DID_INTEL_PTL_H_ID_4, PTL_CORE_4, TDP_25W, PTL_SKU_6, PTL_TDC_3 }, { PCI_DID_INTEL_PTL_H_ID_5, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 }, { PCI_DID_INTEL_PTL_H_ID_6, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 }, - { PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_4, PTL_TDC_5 }, + { PCI_DID_INTEL_PTL_H_ID_7, PTL_CORE_4, TDP_25W, PTL_SKU_7, PTL_TDC_4 }, { PCI_DID_INTEL_PTL_H_ID_8, PTL_CORE_3, TDP_25W, PTL_SKU_2, PTL_TDC_3 }, { PCI_DID_INTEL_WCL_ID_1, WCL_CORE, TDP_15W, WCL_SKU_1, WCL_TDC_1 }, { PCI_DID_INTEL_WCL_ID_2, WCL_CORE, TDP_15W, WCL_SKU_2, WCL_TDC_1 }, diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb index a310a1be3f..e19ca02080 100644 --- a/src/soc/intel/pantherlake/chipset_ptl.cb +++ b/src/soc/intel/pantherlake/chipset_ptl.cb @@ -71,6 +71,13 @@ chip soc/intel/pantherlake [VR_DOMAIN_ATOM] = 30 * 4 }" + register "icc_max[PTL_SKU_7]" = "{ + [VR_DOMAIN_IA] = 90 * 4, + [VR_DOMAIN_GT] = 56 * 4, + [VR_DOMAIN_SA] = 56 * 4, + [VR_DOMAIN_ATOM] = 30 * 4 + }" + register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS" register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000"