diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb index cae73aab43..f05a023bb1 100644 --- a/src/mainboard/amd/birman/devicetree_glinda.cb +++ b/src/mainboard/amd/birman/devicetree_glinda.cb @@ -41,7 +41,7 @@ chip soc/amd/glinda register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb index 3fc1f0dfca..ba18fc51ce 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb @@ -41,7 +41,7 @@ chip soc/amd/phoenix register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index d84a010ec2..9916931545 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -41,7 +41,7 @@ chip soc/amd/phoenix register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 5e92001ae5..5a7fd00c2a 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -41,7 +41,7 @@ chip soc/amd/glinda register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb index afd4ca7edd..2490c9b93b 100644 --- a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb @@ -41,7 +41,7 @@ chip soc/amd/phoenix register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index a186b2d825..9077372ebd 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -39,7 +39,7 @@ chip soc/amd/mendocino register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 898a592261..bd6aeb40e2 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -41,7 +41,7 @@ chip soc/amd/phoenix register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 2fe3e46d97..b58dc2ce8d 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -98,7 +98,7 @@ chip soc/amd/cezanne register "pspp_policy" = "DXIO_PSPP_BALANCED" - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ /* Left USB C0 Port */ .Usb2PhyPort[0] = { diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index f221adcd2a..02444aa59a 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -28,7 +28,7 @@ end chip soc/amd/cezanne - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ /* Left USB C0 Port */ .Usb2PhyPort[0] = { diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 62e19bf75a..97994c7885 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -85,7 +85,7 @@ chip soc/amd/phoenix register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works register "s0ix_enable" = "true" - register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 738282f5c3..bdf6ba8ff1 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -93,7 +93,7 @@ struct soc_amd_cezanne_config { DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; /* eDP phy tuning settings */ diff --git a/src/soc/amd/glinda/chip.h b/src/soc/amd/glinda/chip.h index 085bac5d20..186591f094 100644 --- a/src/soc/amd/glinda/chip.h +++ b/src/soc/amd/glinda/chip.h @@ -103,7 +103,7 @@ struct soc_amd_glinda_config { DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; }; diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index f161038e98..9a805b9246 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -168,7 +168,7 @@ struct soc_amd_mendocino_config { DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal Integrity is highly recommended. */ diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h index 07b0dab7b9..eabd44518e 100644 --- a/src/soc/amd/phoenix/chip.h +++ b/src/soc/amd/phoenix/chip.h @@ -107,7 +107,7 @@ struct soc_amd_phoenix_config { DXIO_PSPP_POWERSAVE, } pspp_policy; - uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; #if !CONFIG(PLATFORM_USES_FSP2_0)