diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index f85c4676cc..1106e3483a 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -140,6 +140,7 @@ void lpc_enable_sio_decode(const bool addr);
 uintptr_t lpc_spibase(void);
 void lpc_tpm_decode(void);
 void lpc_tpm_decode_spi(void);
+void soc_lpc_tpm_decode_spi(void);
 void lpc_enable_rom(void);
 void lpc_enable_spi_prefetch(void);
 uint32_t lpc_get_rom2_region(size_t *bios_size);
diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c
index b796f3faa4..d41ce0cff1 100644
--- a/src/soc/amd/common/block/lpc/lpc_util.c
+++ b/src/soc/amd/common/block/lpc/lpc_util.c
@@ -220,6 +220,8 @@ void lpc_tpm_decode(void)
 	pci_write_config32(_LPCB_DEV, LPC_TRUSTED_PLATFORM_MODULE, value);
 }
 
+void __weak soc_lpc_tpm_decode_spi(void) { }
+
 /*
  * Enable FCH to decode TPM associated Memory and IO regions to SPI
  *
@@ -236,6 +238,8 @@ void lpc_tpm_decode_spi(void)
 					SPI_BASE_ADDRESS_REGISTER);
 	pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, spibase
 					| ROUTE_TPM_2_SPI);
+
+	soc_lpc_tpm_decode_spi();
 }
 
 /*