From 6127a1d19dc6fe61395f0acfefe75173e3cbda14 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 16 Sep 2025 08:20:15 +0200 Subject: [PATCH] amdblock/lpc: Add SoC hook to set up SPI TPM decoding MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some SoCs may require additional programming to get the SPI TPM work properly. This hook is especially needed if mainboard selects TPM_MEASURED_BOOT_INIT_BOOTBLOCK and TPM is initialized before any vendor silicon initialization code runs (FSP or OpenSIL). Change-Id: I90dbcbfb554ac3cfbcf23d708c3440d27959c632 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/89191 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph --- src/soc/amd/common/block/include/amdblocks/lpc.h | 1 + src/soc/amd/common/block/lpc/lpc_util.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index f85c4676cc..1106e3483a 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -140,6 +140,7 @@ void lpc_enable_sio_decode(const bool addr); uintptr_t lpc_spibase(void); void lpc_tpm_decode(void); void lpc_tpm_decode_spi(void); +void soc_lpc_tpm_decode_spi(void); void lpc_enable_rom(void); void lpc_enable_spi_prefetch(void); uint32_t lpc_get_rom2_region(size_t *bios_size); diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index b796f3faa4..d41ce0cff1 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -220,6 +220,8 @@ void lpc_tpm_decode(void) pci_write_config32(_LPCB_DEV, LPC_TRUSTED_PLATFORM_MODULE, value); } +void __weak soc_lpc_tpm_decode_spi(void) { } + /* * Enable FCH to decode TPM associated Memory and IO regions to SPI * @@ -236,6 +238,8 @@ void lpc_tpm_decode_spi(void) SPI_BASE_ADDRESS_REGISTER); pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, spibase | ROUTE_TPM_2_SPI); + + soc_lpc_tpm_decode_spi(); } /*