From 5f86aba4b3795d632a3da9769eaa24a4ea0fd039 Mon Sep 17 00:00:00 2001 From: Wonkyu Kim Date: Mon, 29 Dec 2025 13:35:33 -0800 Subject: [PATCH] soc/intel/common: Enable high address support for MCHBAR in ACPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Increased MHBR field width in ACPI northbridge.asl from 17 to 27 bits, allowing MCHBAR to be set above 4GB (up to 42 bits). Reference: Section 10.3 in 850519 BUG=none TEST=boot to OS with ACPI debug enabled and check GMHB log Signed-off-by: Wonkyu Kim Change-Id: I885ff64598367ddadcec05926af3556024b61250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/90729 Reviewed-by: Kapil Porwal Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/common/block/acpi/acpi/northbridge.asl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/acpi/acpi/northbridge.asl b/src/soc/intel/common/block/acpi/acpi/northbridge.asl index 3b2fb85933..90c90027d0 100644 --- a/src/soc/intel/common/block/acpi/acpi/northbridge.asl +++ b/src/soc/intel/common/block/acpi/acpi/northbridge.asl @@ -24,7 +24,7 @@ Device (MCHC) Offset(0x48), /* MCHBAR (0:0:0:48) */ MHEN, 1, /* Enable */ , 14, - MHBR, 17, /* MCHBAR [31:15] */ + MHBR, 27, /* MCHBAR [41:15] */ Offset(0x60), /* PCIEXBAR (0:0:0:60) */ PXEN, 1, /* Enable */ @@ -246,6 +246,7 @@ Method (_CRS, 0, Serialized) Method (GMHB, 0, Serialized) { Local0 = \_SB.PCI0.MCHC.MHBR << 15 + Printf ("GMHB: %o", ToHexString(Local0)) Return (Local0) }