From 5eb9e9999d986c313b96365b452941434a40441e Mon Sep 17 00:00:00 2001 From: Sowmya V Date: Tue, 17 Feb 2026 16:12:23 +0530 Subject: [PATCH] mb/google/fatcat: Configure CDCLK frequency for display Configure the Core Display Clock (CDCLK) frequency selection by setting the 'vga_cd_clk_freq_sel' register to CD_CLK_461MHZ in the fatcat baseboard devicetree. This ensures the display engine operates at the required frequency for the panel to meet the hardware configuration. BUG=b:458353982 TEST=Build and boot fatcat/lapis, verify display initialization. Change-Id: If8812bc66149b402adb7b9159f3a28d35903b785 Signed-off-by: Sowmya V Reviewed-on: https://review.coreboot.org/c/coreboot/+/91309 Tested-by: build bot (Jenkins) Reviewed-by: Kapil Porwal --- .../google/fatcat/variants/baseboard/fatcat/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index fd1f55fabe..c9b9ddb293 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -141,6 +141,7 @@ chip soc/intel/pantherlake register "pch_hda_idisp_codec_enable" = "true" register "disable_progress_bar" = "true" + register "vga_cd_clk_freq_sel" = "CD_CLK_461MHZ" device domain 0 on device ref dtt on end